75 lines
2.1 KiB
YAML
75 lines
2.1 KiB
YAML
# SPDX-License-Identifier: (GPL-2.0+ OR MIT)
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%YAML 1.2
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---
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$id: http://devicetree.org/schemas/clock/rockchip,rk3228-cru.yaml#
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$schema: http://devicetree.org/meta-schemas/core.yaml#
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title: Rockchip RK3228 Clock and Reset Unit (CRU)
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maintainers:
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- Elaine Zhang <zhangqing@rock-chips.com>
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- Heiko Stuebner <heiko@sntech.de>
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description: |
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The RK3228 clock controller generates and supplies clocks to various
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controllers within the SoC and also implements a reset controller for SoC
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peripherals.
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Each clock is assigned an identifier and client nodes can use this identifier
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to specify the clock which they consume. All available clocks are defined as
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preprocessor macros in the dt-bindings/clock/rk3228-cru.h headers and can be
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used in device tree sources. Similar macros exist for the reset sources in
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these files.
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There are several clocks that are generated outside the SoC. It is expected
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that they are defined using standard clock bindings with following
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clock-output-names:
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- "xin24m" - crystal input - required
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- "ext_i2s" - external I2S clock - optional
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- "ext_gmac" - external GMAC clock - optional
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- "ext_hsadc" - external HSADC clock - optional
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- "phy_50m_out" - output clock of the pll in the mac phy
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properties:
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compatible:
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enum:
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- rockchip,rk3228-cru
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reg:
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maxItems: 1
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"#clock-cells":
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const: 1
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"#reset-cells":
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const: 1
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clocks:
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maxItems: 1
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clock-names:
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const: xin24m
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rockchip,grf:
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$ref: /schemas/types.yaml#/definitions/phandle
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description:
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Phandle to the syscon managing the "general register files" (GRF),
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if missing pll rates are not changeable, due to the missing pll
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lock status.
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required:
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- compatible
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- reg
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- "#clock-cells"
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- "#reset-cells"
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additionalProperties: false
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examples:
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- |
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cru: clock-controller@20000000 {
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compatible = "rockchip,rk3228-cru";
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reg = <0x20000000 0x1000>;
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rockchip,grf = <&grf>;
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#clock-cells = <1>;
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#reset-cells = <1>;
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};
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