186 lines
6.0 KiB
C
186 lines
6.0 KiB
C
// SPDX-License-Identifier: GPL-2.0-or-later
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/*
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* Copyright 2016, Cyril Bur, IBM Corp.
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*
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* Test the kernel's signal frame code.
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*
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* The kernel sets up two sets of ucontexts if the signal was to be
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* delivered while the thread was in a transaction (referred too as
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* first and second contexts).
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* Expected behaviour is that the checkpointed state is in the user
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* context passed to the signal handler (first context). The speculated
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* state can be accessed with the uc_link pointer (second context).
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*
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* The rationale for this is that if TM unaware code (which linked
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* against TM libs) installs a signal handler it will not know of the
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* speculative nature of the 'live' registers and may infer the wrong
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* thing.
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*/
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#include <stdlib.h>
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#include <stdio.h>
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#include <string.h>
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#include <signal.h>
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#include <unistd.h>
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#include <altivec.h>
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#include "utils.h"
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#include "tm.h"
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#define MAX_ATTEMPT 500000
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#define NV_VSX_REGS 12 /* Number of VSX registers to check. */
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#define VSX20 20 /* First VSX register to check in vsr20-vsr31 subset */
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#define FPR20 20 /* FPR20 overlaps VSX20 most significant doubleword */
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long tm_signal_self_context_load(pid_t pid, long *gprs, double *fps, vector int *vms, vector int *vss);
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static sig_atomic_t fail, broken;
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/* Test only 12 vsx registers from vsr20 to vsr31 */
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vector int vsxs[] = {
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/* First context will be set with these values, i.e. non-speculative */
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/* VSX20 , VSX21 , ... */
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{ 1, 2, 3, 4},{ 5, 6, 7, 8},{ 9,10,11,12},
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{13,14,15,16},{17,18,19,20},{21,22,23,24},
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{25,26,27,28},{29,30,31,32},{33,34,35,36},
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{37,38,39,40},{41,42,43,44},{45,46,47,48},
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/* Second context will be set with these values, i.e. speculative */
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/* VSX20 , VSX21 , ... */
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{-1, -2, -3, -4 },{-5, -6, -7, -8 },{-9, -10,-11,-12},
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{-13,-14,-15,-16},{-17,-18,-19,-20},{-21,-22,-23,-24},
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{-25,-26,-27,-28},{-29,-30,-31,-32},{-33,-34,-35,-36},
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{-37,-38,-39,-40},{-41,-42,-43,-44},{-45,-46,-47,-48}
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};
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static void signal_usr1(int signum, siginfo_t *info, void *uc)
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{
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int i, j;
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uint8_t vsx[sizeof(vector int)];
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uint8_t vsx_tm[sizeof(vector int)];
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ucontext_t *ucp = uc;
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ucontext_t *tm_ucp = ucp->uc_link;
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/*
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* FP registers and VMX registers overlap the VSX registers.
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*
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* FP registers (f0-31) overlap the most significant 64 bits of VSX
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* registers vsr0-31, whilst VMX registers vr0-31, being 128-bit like
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* the VSX registers, overlap fully the other half of VSX registers,
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* i.e. vr0-31 overlaps fully vsr32-63.
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*
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* Due to compatibility and historical reasons (VMX/Altivec support
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* appeared first on the architecture), VMX registers vr0-31 (so VSX
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* half vsr32-63 too) are stored right after the v_regs pointer, in an
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* area allocated for 'vmx_reverse' array (please see
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* arch/powerpc/include/uapi/asm/sigcontext.h for details about the
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* mcontext_t structure on Power).
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*
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* The other VSX half (vsr0-31) is hence stored below vr0-31/vsr32-63
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* registers, but only the least significant 64 bits of vsr0-31. The
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* most significant 64 bits of vsr0-31 (f0-31), as it overlaps the FP
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* registers, is kept in fp_regs.
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*
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* v_regs is a 16 byte aligned pointer at the start of vmx_reserve
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* (vmx_reserve may or may not be 16 aligned) where the v_regs structure
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* exists, so v_regs points to where vr0-31 / vsr32-63 registers are
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* fully stored. Since v_regs type is elf_vrregset_t, v_regs + 1
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* skips all the slots used to store vr0-31 / vsr32-64 and points to
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* part of one VSX half, i.e. v_regs + 1 points to the least significant
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* 64 bits of vsr0-31. The other part of this half (the most significant
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* part of vsr0-31) is stored in fp_regs.
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*
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*/
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/* Get pointer to least significant doubleword of vsr0-31 */
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long *vsx_ptr = (long *)(ucp->uc_mcontext.v_regs + 1);
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long *tm_vsx_ptr = (long *)(tm_ucp->uc_mcontext.v_regs + 1);
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/* Check first context. Print all mismatches. */
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for (i = 0; i < NV_VSX_REGS; i++) {
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/*
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* Copy VSX most significant doubleword from fp_regs and
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* copy VSX least significant one from 64-bit slots below
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* saved VMX registers.
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*/
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memcpy(vsx, &ucp->uc_mcontext.fp_regs[FPR20 + i], 8);
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memcpy(vsx + 8, &vsx_ptr[VSX20 + i], 8);
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fail = memcmp(vsx, &vsxs[i], sizeof(vector int));
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if (fail) {
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broken = 1;
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printf("VSX%d (1st context) == 0x", VSX20 + i);
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for (j = 0; j < 16; j++)
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printf("%02x", vsx[j]);
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printf(" instead of 0x");
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for (j = 0; j < 4; j++)
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printf("%08x", vsxs[i][j]);
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printf(" (expected)\n");
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}
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}
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/* Check second context. Print all mismatches. */
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for (i = 0; i < NV_VSX_REGS; i++) {
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/*
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* Copy VSX most significant doubleword from fp_regs and
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* copy VSX least significant one from 64-bit slots below
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* saved VMX registers.
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*/
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memcpy(vsx_tm, &tm_ucp->uc_mcontext.fp_regs[FPR20 + i], 8);
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memcpy(vsx_tm + 8, &tm_vsx_ptr[VSX20 + i], 8);
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fail = memcmp(vsx_tm, &vsxs[NV_VSX_REGS + i], sizeof(vector int));
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if (fail) {
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broken = 1;
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printf("VSX%d (2nd context) == 0x", VSX20 + i);
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for (j = 0; j < 16; j++)
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printf("%02x", vsx_tm[j]);
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printf(" instead of 0x");
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for (j = 0; j < 4; j++)
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printf("%08x", vsxs[NV_VSX_REGS + i][j]);
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printf("(expected)\n");
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}
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}
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}
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static int tm_signal_context_chk()
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{
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struct sigaction act;
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int i;
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long rc;
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pid_t pid = getpid();
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SKIP_IF(!have_htm());
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SKIP_IF(htm_is_synthetic());
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act.sa_sigaction = signal_usr1;
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sigemptyset(&act.sa_mask);
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act.sa_flags = SA_SIGINFO;
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if (sigaction(SIGUSR1, &act, NULL) < 0) {
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perror("sigaction sigusr1");
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exit(1);
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}
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i = 0;
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while (i < MAX_ATTEMPT && !broken) {
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/*
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* tm_signal_self_context_load will set both first and second
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* contexts accordingly to the values passed through non-NULL
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* array pointers to it, in that case 'vsxs', and invoke the
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* signal handler installed for SIGUSR1.
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*/
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rc = tm_signal_self_context_load(pid, NULL, NULL, NULL, vsxs);
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FAIL_IF(rc != pid);
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i++;
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}
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return (broken);
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}
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int main(void)
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{
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return test_harness(tm_signal_context_chk, "tm_signal_context_chk_vsx");
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}
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