170 lines
4.1 KiB
C
170 lines
4.1 KiB
C
// SPDX-License-Identifier: GPL-2.0-only
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/*
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* aarch32_id_regs - Test for ID register behavior on AArch64-only systems
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*
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* Copyright (c) 2022 Google LLC.
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*
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* Test that KVM handles the AArch64 views of the AArch32 ID registers as RAZ
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* and WI from userspace.
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*/
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#include <stdint.h>
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#include "kvm_util.h"
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#include "processor.h"
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#include "test_util.h"
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#define BAD_ID_REG_VAL 0x1badc0deul
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#define GUEST_ASSERT_REG_RAZ(reg) GUEST_ASSERT_EQ(read_sysreg_s(reg), 0)
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static void guest_main(void)
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{
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GUEST_ASSERT_REG_RAZ(SYS_ID_PFR0_EL1);
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GUEST_ASSERT_REG_RAZ(SYS_ID_PFR1_EL1);
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GUEST_ASSERT_REG_RAZ(SYS_ID_DFR0_EL1);
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GUEST_ASSERT_REG_RAZ(SYS_ID_AFR0_EL1);
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GUEST_ASSERT_REG_RAZ(SYS_ID_MMFR0_EL1);
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GUEST_ASSERT_REG_RAZ(SYS_ID_MMFR1_EL1);
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GUEST_ASSERT_REG_RAZ(SYS_ID_MMFR2_EL1);
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GUEST_ASSERT_REG_RAZ(SYS_ID_MMFR3_EL1);
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GUEST_ASSERT_REG_RAZ(SYS_ID_ISAR0_EL1);
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GUEST_ASSERT_REG_RAZ(SYS_ID_ISAR1_EL1);
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GUEST_ASSERT_REG_RAZ(SYS_ID_ISAR2_EL1);
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GUEST_ASSERT_REG_RAZ(SYS_ID_ISAR3_EL1);
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GUEST_ASSERT_REG_RAZ(SYS_ID_ISAR4_EL1);
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GUEST_ASSERT_REG_RAZ(SYS_ID_ISAR5_EL1);
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GUEST_ASSERT_REG_RAZ(SYS_ID_MMFR4_EL1);
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GUEST_ASSERT_REG_RAZ(SYS_ID_ISAR6_EL1);
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GUEST_ASSERT_REG_RAZ(SYS_MVFR0_EL1);
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GUEST_ASSERT_REG_RAZ(SYS_MVFR1_EL1);
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GUEST_ASSERT_REG_RAZ(SYS_MVFR2_EL1);
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GUEST_ASSERT_REG_RAZ(sys_reg(3, 0, 0, 3, 3));
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GUEST_ASSERT_REG_RAZ(SYS_ID_PFR2_EL1);
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GUEST_ASSERT_REG_RAZ(SYS_ID_DFR1_EL1);
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GUEST_ASSERT_REG_RAZ(SYS_ID_MMFR5_EL1);
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GUEST_ASSERT_REG_RAZ(sys_reg(3, 0, 0, 3, 7));
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GUEST_DONE();
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}
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static void test_guest_raz(struct kvm_vcpu *vcpu)
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{
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struct ucall uc;
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vcpu_run(vcpu);
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switch (get_ucall(vcpu, &uc)) {
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case UCALL_ABORT:
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REPORT_GUEST_ASSERT(uc);
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break;
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case UCALL_DONE:
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break;
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default:
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TEST_FAIL("Unexpected ucall: %lu", uc.cmd);
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}
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}
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static uint64_t raz_wi_reg_ids[] = {
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KVM_ARM64_SYS_REG(SYS_ID_PFR0_EL1),
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KVM_ARM64_SYS_REG(SYS_ID_PFR1_EL1),
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KVM_ARM64_SYS_REG(SYS_ID_DFR0_EL1),
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KVM_ARM64_SYS_REG(SYS_ID_MMFR0_EL1),
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KVM_ARM64_SYS_REG(SYS_ID_MMFR1_EL1),
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KVM_ARM64_SYS_REG(SYS_ID_MMFR2_EL1),
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KVM_ARM64_SYS_REG(SYS_ID_MMFR3_EL1),
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KVM_ARM64_SYS_REG(SYS_ID_ISAR0_EL1),
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KVM_ARM64_SYS_REG(SYS_ID_ISAR1_EL1),
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KVM_ARM64_SYS_REG(SYS_ID_ISAR2_EL1),
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KVM_ARM64_SYS_REG(SYS_ID_ISAR3_EL1),
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KVM_ARM64_SYS_REG(SYS_ID_ISAR4_EL1),
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KVM_ARM64_SYS_REG(SYS_ID_ISAR5_EL1),
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KVM_ARM64_SYS_REG(SYS_ID_MMFR4_EL1),
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KVM_ARM64_SYS_REG(SYS_ID_ISAR6_EL1),
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KVM_ARM64_SYS_REG(SYS_MVFR0_EL1),
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KVM_ARM64_SYS_REG(SYS_MVFR1_EL1),
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KVM_ARM64_SYS_REG(SYS_MVFR2_EL1),
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KVM_ARM64_SYS_REG(SYS_ID_PFR2_EL1),
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KVM_ARM64_SYS_REG(SYS_ID_MMFR5_EL1),
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};
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static void test_user_raz_wi(struct kvm_vcpu *vcpu)
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{
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int i;
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for (i = 0; i < ARRAY_SIZE(raz_wi_reg_ids); i++) {
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uint64_t reg_id = raz_wi_reg_ids[i];
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uint64_t val;
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vcpu_get_reg(vcpu, reg_id, &val);
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ASSERT_EQ(val, 0);
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/*
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* Expect the ioctl to succeed with no effect on the register
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* value.
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*/
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vcpu_set_reg(vcpu, reg_id, BAD_ID_REG_VAL);
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vcpu_get_reg(vcpu, reg_id, &val);
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ASSERT_EQ(val, 0);
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}
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}
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static uint64_t raz_invariant_reg_ids[] = {
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KVM_ARM64_SYS_REG(SYS_ID_AFR0_EL1),
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KVM_ARM64_SYS_REG(sys_reg(3, 0, 0, 3, 3)),
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KVM_ARM64_SYS_REG(SYS_ID_DFR1_EL1),
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KVM_ARM64_SYS_REG(sys_reg(3, 0, 0, 3, 7)),
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};
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static void test_user_raz_invariant(struct kvm_vcpu *vcpu)
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{
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int i, r;
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for (i = 0; i < ARRAY_SIZE(raz_invariant_reg_ids); i++) {
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uint64_t reg_id = raz_invariant_reg_ids[i];
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uint64_t val;
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vcpu_get_reg(vcpu, reg_id, &val);
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ASSERT_EQ(val, 0);
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r = __vcpu_set_reg(vcpu, reg_id, BAD_ID_REG_VAL);
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TEST_ASSERT(r < 0 && errno == EINVAL,
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"unexpected KVM_SET_ONE_REG error: r=%d, errno=%d", r, errno);
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vcpu_get_reg(vcpu, reg_id, &val);
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ASSERT_EQ(val, 0);
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}
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}
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static bool vcpu_aarch64_only(struct kvm_vcpu *vcpu)
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{
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uint64_t val, el0;
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vcpu_get_reg(vcpu, KVM_ARM64_SYS_REG(SYS_ID_AA64PFR0_EL1), &val);
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el0 = (val & ARM64_FEATURE_MASK(ID_AA64PFR0_EL0)) >> ID_AA64PFR0_EL0_SHIFT;
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return el0 == ID_AA64PFR0_ELx_64BIT_ONLY;
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}
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int main(void)
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{
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struct kvm_vcpu *vcpu;
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struct kvm_vm *vm;
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vm = vm_create_with_one_vcpu(&vcpu, guest_main);
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TEST_REQUIRE(vcpu_aarch64_only(vcpu));
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ucall_init(vm, NULL);
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test_user_raz_wi(vcpu);
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test_user_raz_invariant(vcpu);
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test_guest_raz(vcpu);
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ucall_uninit(vm);
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kvm_vm_free(vm);
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}
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