248 lines
11 KiB
JSON
248 lines
11 KiB
JSON
[
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{
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"Unit": "CPU-M-CF",
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"EventCode": "128",
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"EventName": "DTLB1_MISSES",
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"BriefDescription": "DTLB1 Misses",
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"PublicDescription": "Level-1 Data TLB miss in progress. Incremented by one for every cycle a DTLB1 miss is in progress."
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},
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{
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"Unit": "CPU-M-CF",
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"EventCode": "129",
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"EventName": "ITLB1_MISSES",
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"BriefDescription": "ITLB1 Misses",
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"PublicDescription": "Level-1 Instruction TLB miss in progress. Incremented by one for every cycle a ITLB1 miss is in progress."
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},
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{
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"Unit": "CPU-M-CF",
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"EventCode": "130",
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"EventName": "L1D_L2I_SOURCED_WRITES",
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"BriefDescription": "L1D L2I Sourced Writes",
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"PublicDescription": "A directory write to the Level-1 Data cache directory where the returned cache line was sourced from the Level-2 Instruction cache."
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},
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{
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"Unit": "CPU-M-CF",
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"EventCode": "131",
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"EventName": "L1I_L2I_SOURCED_WRITES",
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"BriefDescription": "L1I L2I Sourced Writes",
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"PublicDescription": "A directory write to the Level-1 Instruction cache directory where the returned cache line was sourced from the Level-2 Instruction cache."
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},
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{
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"Unit": "CPU-M-CF",
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"EventCode": "132",
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"EventName": "L1D_L2D_SOURCED_WRITES",
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"BriefDescription": "L1D L2D Sourced Writes",
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"PublicDescription": "A directory write to the Level-1 Data cache directory where the returned cache line was sourced from the Level-2 Data cache."
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},
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{
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"Unit": "CPU-M-CF",
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"EventCode": "133",
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"EventName": "DTLB1_WRITES",
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"BriefDescription": "DTLB1 Writes",
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"PublicDescription": "A translation entry has been written to the Level-1 Data Translation Lookaside Buffer (DTLB1)."
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},
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{
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"Unit": "CPU-M-CF",
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"EventCode": "135",
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"EventName": "L1D_LMEM_SOURCED_WRITES",
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"BriefDescription": "L1D Local Memory Sourced Writes",
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"PublicDescription": "A directory write to the Level-1 Data cache where the installed cache line was sourced from memory that is attached to the same book as the Data cache (Local Memory)."
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},
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{
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"Unit": "CPU-M-CF",
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"EventCode": "137",
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"EventName": "L1I_LMEM_SOURCED_WRITES",
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"BriefDescription": "L1I Local Memory Sourced Writes",
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"PublicDescription": "A directory write to the Level-1 Instruction cache where the installed cache line was sourced from memory that is attached to the same book as the Instruction cache (Local Memory)."
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},
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{
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"Unit": "CPU-M-CF",
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"EventCode": "138",
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"EventName": "L1D_RO_EXCL_WRITES",
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"BriefDescription": "L1D Read-only Exclusive Writes",
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"PublicDescription": "A directory write to the Level-1 Data Cache where the line was originally in a Read-Only state in the cache but has been updated to be in the Exclusive state that allows stores to the cache line."
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},
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{
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"Unit": "CPU-M-CF",
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"EventCode": "139",
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"EventName": "DTLB1_HPAGE_WRITES",
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"BriefDescription": "DTLB1 One-Megabyte Page Writes",
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"PublicDescription": "A translation entry has been written to the Level-1 Data Translation Lookaside Buffer for a one-megabyte page."
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},
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{
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"Unit": "CPU-M-CF",
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"EventCode": "140",
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"EventName": "ITLB1_WRITES",
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"BriefDescription": "ITLB1 Writes",
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"PublicDescription": "A translation entry has been written to the Level-1 Instruction Translation Lookaside Buffer (ITLB1)."
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},
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{
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"Unit": "CPU-M-CF",
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"EventCode": "141",
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"EventName": "TLB2_PTE_WRITES",
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"BriefDescription": "TLB2 PTE Writes",
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"PublicDescription": "A translation entry has been written to the Level-2 TLB Page Table Entry arrays."
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},
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{
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"Unit": "CPU-M-CF",
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"EventCode": "142",
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"EventName": "TLB2_CRSTE_HPAGE_WRITES",
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"BriefDescription": "TLB2 CRSTE One-Megabyte Page Writes",
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"PublicDescription": "A translation entry has been written to the Level-2 TLB Common Region Segment Table Entry arrays for a one-megabyte large page translation."
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},
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{
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"Unit": "CPU-M-CF",
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"EventCode": "143",
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"EventName": "TLB2_CRSTE_WRITES",
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"BriefDescription": "TLB2 CRSTE Writes",
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"PublicDescription": "A translation entry has been written to the Level-2 TLB Common Region Segment Table Entry arrays."
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},
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{
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"Unit": "CPU-M-CF",
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"EventCode": "144",
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"EventName": "L1D_ONCHIP_L3_SOURCED_WRITES",
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"BriefDescription": "L1D On-Chip L3 Sourced Writes",
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"PublicDescription": "A directory write to the Level-1 Data cache directory where the returned cache line was sourced from an On Chip Level-3 cache without intervention."
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},
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{
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"Unit": "CPU-M-CF",
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"EventCode": "145",
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"EventName": "L1D_OFFCHIP_L3_SOURCED_WRITES",
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"BriefDescription": "L1D Off-Chip L3 Sourced Writes",
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"PublicDescription": "A directory write to the Level-1 Data cache directory where the returned cache line was sourced from an Off Chip/On Book Level-3 cache without intervention."
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},
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{
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"Unit": "CPU-M-CF",
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"EventCode": "146",
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"EventName": "L1D_OFFBOOK_L3_SOURCED_WRITES",
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"BriefDescription": "L1D Off-Book L3 Sourced Writes",
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"PublicDescription": "A directory write to the Level-1 Data cache directory where the returned cache line was sourced from an Off Book Level-3 cache without intervention."
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},
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{
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"Unit": "CPU-M-CF",
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"EventCode": "147",
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"EventName": "L1D_ONBOOK_L4_SOURCED_WRITES",
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"BriefDescription": "L1D On-Book L4 Sourced Writes",
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"PublicDescription": "A directory write to the Level-1 Data cache directory where the returned cache line was sourced from an On Book Level-4 cache."
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},
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{
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"Unit": "CPU-M-CF",
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"EventCode": "148",
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"EventName": "L1D_OFFBOOK_L4_SOURCED_WRITES",
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"BriefDescription": "L1D Off-Book L4 Sourced Writes",
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"PublicDescription": "A directory write to the Level-1 Data cache directory where the returned cache line was sourced from an Off Book Level-4 cache."
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},
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{
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"Unit": "CPU-M-CF",
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"EventCode": "149",
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"EventName": "TX_NC_TEND",
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"BriefDescription": "Completed TEND instructions in non-constrained TX mode",
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"PublicDescription": "A TEND instruction has completed in a nonconstrained transactional-execution mode."
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},
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{
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"Unit": "CPU-M-CF",
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"EventCode": "150",
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"EventName": "L1D_ONCHIP_L3_SOURCED_WRITES_IV",
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"BriefDescription": "L1D On-Chip L3 Sourced Writes with Intervention",
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"PublicDescription": "A directory write to the Level-1 Data cache directory where the returned cache line was sourced from a On Chip Level-3 cache with intervention."
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},
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{
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"Unit": "CPU-M-CF",
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"EventCode": "151",
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"EventName": "L1D_OFFCHIP_L3_SOURCED_WRITES_IV",
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"BriefDescription": "L1D Off-Chip L3 Sourced Writes with Intervention",
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"PublicDescription": "A directory write to the Level-1 Data cache directory where the returned cache line was sourced from an Off Chip/On Book Level-3 cache with intervention."
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},
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{
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"Unit": "CPU-M-CF",
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"EventCode": "152",
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"EventName": "L1D_OFFBOOK_L3_SOURCED_WRITES_IV",
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"BriefDescription": "L1D Off-Book L3 Sourced Writes with Intervention",
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"PublicDescription": "A directory write to the Level-1 Data cache directory where the returned cache line was sourced from an Off Book Level-3 cache with intervention."
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},
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{
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"Unit": "CPU-M-CF",
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"EventCode": "153",
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"EventName": "L1I_ONCHIP_L3_SOURCED_WRITES",
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"BriefDescription": "L1I On-Chip L3 Sourced Writes",
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"PublicDescription": "A directory write to the Level-1 Instruction cache directory where the returned cache line was sourced from an On Chip Level-3 cache without intervention."
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},
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{
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"Unit": "CPU-M-CF",
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"EventCode": "154",
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"EventName": "L1I_OFFCHIP_L3_SOURCED_WRITES",
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"BriefDescription": "L1I Off-Chip L3 Sourced Writes",
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"PublicDescription": "A directory write to the Level-1 Instruction cache directory where the returned cache line was sourced from an Off Chip/On Book Level-3 cache without intervention."
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},
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{
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"Unit": "CPU-M-CF",
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"EventCode": "155",
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"EventName": "L1I_OFFBOOK_L3_SOURCED_WRITES",
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"BriefDescription": "L1I Off-Book L3 Sourced Writes",
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"PublicDescription": "A directory write to the Level-1 Instruction cache directory where the returned cache line was sourced from an Off Book Level-3 cache without intervention."
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},
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{
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"Unit": "CPU-M-CF",
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"EventCode": "156",
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"EventName": "L1I_ONBOOK_L4_SOURCED_WRITES",
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"BriefDescription": "L1I On-Book L4 Sourced Writes",
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"PublicDescription": "A directory write to the Level-1 Instruction cache directory where the returned cache line was sourced from an On Book Level-4 cache."
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},
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{
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"Unit": "CPU-M-CF",
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"EventCode": "157",
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"EventName": "L1I_OFFBOOK_L4_SOURCED_WRITES",
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"BriefDescription": "L1I Off-Book L4 Sourced Writes",
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"PublicDescription": "A directory write to the Level-1 Instruction cache directory where the returned cache line was sourced from an Off Book Level-4 cache."
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},
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{
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"Unit": "CPU-M-CF",
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"EventCode": "158",
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"EventName": "TX_C_TEND",
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"BriefDescription": "Completed TEND instructions in constrained TX mode",
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"PublicDescription": "A TEND instruction has completed in a constrained transactional-execution mode."
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},
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{
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"Unit": "CPU-M-CF",
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"EventCode": "159",
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"EventName": "L1I_ONCHIP_L3_SOURCED_WRITES_IV",
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"BriefDescription": "L1I On-Chip L3 Sourced Writes with Intervention",
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"PublicDescription": "A directory write to the Level-1 Instruction cache directory where the returned cache line was sourced from an On Chip Level-3 cache with intervention."
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},
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{
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"Unit": "CPU-M-CF",
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"EventCode": "160",
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"EventName": "L1I_OFFCHIP_L3_SOURCED_WRITES_IV",
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"BriefDescription": "L1I Off-Chip L3 Sourced Writes with Intervention",
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"PublicDescription": "A directory write to the Level-1 Instruction cache directory where the returned cache line was sourced from an Off Chip/On Book Level-3 cache with intervention."
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},
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{
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"Unit": "CPU-M-CF",
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"EventCode": "161",
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"EventName": "L1I_OFFBOOK_L3_SOURCED_WRITES_IV",
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"BriefDescription": "L1I Off-Book L3 Sourced Writes with Intervention",
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"PublicDescription": "A directory write to the Level-1 Instruction cache directory where the returned cache line was sourced from an Off Book Level-3 cache with intervention."
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},
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{
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"Unit": "CPU-M-CF",
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"EventCode": "177",
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"EventName": "TX_NC_TABORT",
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"BriefDescription": "Aborted transactions in non-constrained TX mode",
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"PublicDescription": "A transaction abort has occurred in a nonconstrained transactional-execution mode."
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},
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{
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"Unit": "CPU-M-CF",
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"EventCode": "178",
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"EventName": "TX_C_TABORT_NO_SPECIAL",
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"BriefDescription": "Aborted transactions in constrained TX mode not using special completion logic",
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"PublicDescription": "A transaction abort has occurred in a constrained transactional-execution mode and the CPU is not using any special logic to allow the transaction to complete."
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},
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{
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"Unit": "CPU-M-CF",
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"EventCode": "179",
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"EventName": "TX_C_TABORT_SPECIAL",
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"BriefDescription": "Aborted transactions in constrained TX mode using special completion logic",
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"PublicDescription": "A transaction abort has occurred in a constrained transactional-execution mode and the CPU is using special logic to allow the transaction to complete."
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}
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]
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