331 lines
7.8 KiB
C
331 lines
7.8 KiB
C
// SPDX-License-Identifier: GPL-2.0-only
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//
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// Copyright(c) 2021-2022 Intel Corporation. All rights reserved.
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//
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// Authors: Cezary Rojewski <cezary.rojewski@intel.com>
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// Amadeusz Slawinski <amadeuszx.slawinski@linux.intel.com>
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//
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#include <sound/hdaudio_ext.h>
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#include "avs.h"
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#include "registers.h"
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#include "trace.h"
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#define AVS_ADSPCS_INTERVAL_US 500
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#define AVS_ADSPCS_TIMEOUT_US 50000
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#define AVS_ADSPCS_DELAY_US 1000
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int avs_dsp_core_power(struct avs_dev *adev, u32 core_mask, bool power)
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{
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u32 value, mask, reg;
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int ret;
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value = snd_hdac_adsp_readl(adev, AVS_ADSP_REG_ADSPCS);
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trace_avs_dsp_core_op(value, core_mask, "power", power);
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mask = AVS_ADSPCS_SPA_MASK(core_mask);
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value = power ? mask : 0;
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snd_hdac_adsp_updatel(adev, AVS_ADSP_REG_ADSPCS, mask, value);
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/* Delay the polling to avoid false positives. */
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usleep_range(AVS_ADSPCS_DELAY_US, 2 * AVS_ADSPCS_DELAY_US);
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mask = AVS_ADSPCS_CPA_MASK(core_mask);
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value = power ? mask : 0;
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ret = snd_hdac_adsp_readl_poll(adev, AVS_ADSP_REG_ADSPCS,
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reg, (reg & mask) == value,
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AVS_ADSPCS_INTERVAL_US,
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AVS_ADSPCS_TIMEOUT_US);
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if (ret)
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dev_err(adev->dev, "core_mask %d power %s failed: %d\n",
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core_mask, power ? "on" : "off", ret);
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return ret;
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}
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int avs_dsp_core_reset(struct avs_dev *adev, u32 core_mask, bool reset)
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{
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u32 value, mask, reg;
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int ret;
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value = snd_hdac_adsp_readl(adev, AVS_ADSP_REG_ADSPCS);
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trace_avs_dsp_core_op(value, core_mask, "reset", reset);
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mask = AVS_ADSPCS_CRST_MASK(core_mask);
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value = reset ? mask : 0;
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snd_hdac_adsp_updatel(adev, AVS_ADSP_REG_ADSPCS, mask, value);
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ret = snd_hdac_adsp_readl_poll(adev, AVS_ADSP_REG_ADSPCS,
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reg, (reg & mask) == value,
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AVS_ADSPCS_INTERVAL_US,
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AVS_ADSPCS_TIMEOUT_US);
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if (ret)
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dev_err(adev->dev, "core_mask %d %s reset failed: %d\n",
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core_mask, reset ? "enter" : "exit", ret);
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return ret;
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}
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int avs_dsp_core_stall(struct avs_dev *adev, u32 core_mask, bool stall)
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{
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u32 value, mask, reg;
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int ret;
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value = snd_hdac_adsp_readl(adev, AVS_ADSP_REG_ADSPCS);
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trace_avs_dsp_core_op(value, core_mask, "stall", stall);
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mask = AVS_ADSPCS_CSTALL_MASK(core_mask);
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value = stall ? mask : 0;
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snd_hdac_adsp_updatel(adev, AVS_ADSP_REG_ADSPCS, mask, value);
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ret = snd_hdac_adsp_readl_poll(adev, AVS_ADSP_REG_ADSPCS,
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reg, (reg & mask) == value,
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AVS_ADSPCS_INTERVAL_US,
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AVS_ADSPCS_TIMEOUT_US);
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if (ret) {
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dev_err(adev->dev, "core_mask %d %sstall failed: %d\n",
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core_mask, stall ? "" : "un", ret);
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return ret;
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}
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/* Give HW time to propagate the change. */
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usleep_range(AVS_ADSPCS_DELAY_US, 2 * AVS_ADSPCS_DELAY_US);
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return 0;
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}
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int avs_dsp_core_enable(struct avs_dev *adev, u32 core_mask)
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{
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int ret;
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ret = avs_dsp_op(adev, power, core_mask, true);
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if (ret)
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return ret;
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ret = avs_dsp_op(adev, reset, core_mask, false);
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if (ret)
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return ret;
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return avs_dsp_op(adev, stall, core_mask, false);
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}
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int avs_dsp_core_disable(struct avs_dev *adev, u32 core_mask)
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{
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/* No error checks to allow for complete DSP shutdown. */
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avs_dsp_op(adev, stall, core_mask, true);
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avs_dsp_op(adev, reset, core_mask, true);
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return avs_dsp_op(adev, power, core_mask, false);
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}
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static int avs_dsp_enable(struct avs_dev *adev, u32 core_mask)
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{
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u32 mask;
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int ret;
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ret = avs_dsp_core_enable(adev, core_mask);
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if (ret < 0)
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return ret;
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mask = core_mask & ~AVS_MAIN_CORE_MASK;
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if (!mask)
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/*
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* without main core, fw is dead anyway
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* so setting D0 for it is futile.
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*/
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return 0;
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ret = avs_ipc_set_dx(adev, mask, true);
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return AVS_IPC_RET(ret);
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}
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static int avs_dsp_disable(struct avs_dev *adev, u32 core_mask)
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{
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int ret;
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ret = avs_ipc_set_dx(adev, core_mask, false);
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if (ret)
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return AVS_IPC_RET(ret);
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return avs_dsp_core_disable(adev, core_mask);
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}
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static int avs_dsp_get_core(struct avs_dev *adev, u32 core_id)
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{
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u32 mask;
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int ret;
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mask = BIT_MASK(core_id);
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if (mask == AVS_MAIN_CORE_MASK)
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/* nothing to do for main core */
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return 0;
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if (core_id >= adev->hw_cfg.dsp_cores) {
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ret = -EINVAL;
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goto err;
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}
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adev->core_refs[core_id]++;
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if (adev->core_refs[core_id] == 1) {
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/*
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* No cores other than main-core can be running for DSP
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* to achieve d0ix. Conscious SET_D0IX IPC failure is permitted,
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* simply d0ix power state will no longer be attempted.
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*/
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ret = avs_dsp_disable_d0ix(adev);
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if (ret && ret != -AVS_EIPC)
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goto err_disable_d0ix;
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ret = avs_dsp_enable(adev, mask);
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if (ret)
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goto err_enable_dsp;
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}
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return 0;
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err_enable_dsp:
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avs_dsp_enable_d0ix(adev);
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err_disable_d0ix:
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adev->core_refs[core_id]--;
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err:
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dev_err(adev->dev, "get core %d failed: %d\n", core_id, ret);
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return ret;
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}
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static int avs_dsp_put_core(struct avs_dev *adev, u32 core_id)
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{
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u32 mask;
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int ret;
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mask = BIT_MASK(core_id);
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if (mask == AVS_MAIN_CORE_MASK)
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/* nothing to do for main core */
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return 0;
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if (core_id >= adev->hw_cfg.dsp_cores) {
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ret = -EINVAL;
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goto err;
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}
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adev->core_refs[core_id]--;
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if (!adev->core_refs[core_id]) {
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ret = avs_dsp_disable(adev, mask);
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if (ret)
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goto err;
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/* Match disable_d0ix in avs_dsp_get_core(). */
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avs_dsp_enable_d0ix(adev);
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}
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return 0;
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err:
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dev_err(adev->dev, "put core %d failed: %d\n", core_id, ret);
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return ret;
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}
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int avs_dsp_init_module(struct avs_dev *adev, u16 module_id, u8 ppl_instance_id,
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u8 core_id, u8 domain, void *param, u32 param_size,
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u16 *instance_id)
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{
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struct avs_module_entry mentry;
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bool was_loaded = false;
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int ret, id;
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id = avs_module_id_alloc(adev, module_id);
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if (id < 0)
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return id;
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ret = avs_get_module_id_entry(adev, module_id, &mentry);
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if (ret)
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goto err_mod_entry;
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ret = avs_dsp_get_core(adev, core_id);
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if (ret)
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goto err_mod_entry;
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/* Load code into memory if this is the first instance. */
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if (!id && !avs_module_entry_is_loaded(&mentry)) {
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ret = avs_dsp_op(adev, transfer_mods, true, &mentry, 1);
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if (ret) {
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dev_err(adev->dev, "load modules failed: %d\n", ret);
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goto err_mod_entry;
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}
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was_loaded = true;
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}
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ret = avs_ipc_init_instance(adev, module_id, id, ppl_instance_id,
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core_id, domain, param, param_size);
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if (ret) {
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ret = AVS_IPC_RET(ret);
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goto err_ipc;
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}
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*instance_id = id;
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return 0;
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err_ipc:
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if (was_loaded)
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avs_dsp_op(adev, transfer_mods, false, &mentry, 1);
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avs_dsp_put_core(adev, core_id);
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err_mod_entry:
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avs_module_id_free(adev, module_id, id);
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return ret;
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}
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void avs_dsp_delete_module(struct avs_dev *adev, u16 module_id, u16 instance_id,
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u8 ppl_instance_id, u8 core_id)
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{
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struct avs_module_entry mentry;
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int ret;
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/* Modules not owned by any pipeline need to be freed explicitly. */
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if (ppl_instance_id == INVALID_PIPELINE_ID)
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avs_ipc_delete_instance(adev, module_id, instance_id);
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avs_module_id_free(adev, module_id, instance_id);
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ret = avs_get_module_id_entry(adev, module_id, &mentry);
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/* Unload occupied memory if this was the last instance. */
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if (!ret && mentry.type.load_type == AVS_MODULE_LOAD_TYPE_LOADABLE) {
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if (avs_is_module_ida_empty(adev, module_id)) {
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ret = avs_dsp_op(adev, transfer_mods, false, &mentry, 1);
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if (ret)
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dev_err(adev->dev, "unload modules failed: %d\n", ret);
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}
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}
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avs_dsp_put_core(adev, core_id);
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}
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int avs_dsp_create_pipeline(struct avs_dev *adev, u16 req_size, u8 priority,
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bool lp, u16 attributes, u8 *instance_id)
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{
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struct avs_fw_cfg *fw_cfg = &adev->fw_cfg;
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int ret, id;
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id = ida_alloc_max(&adev->ppl_ida, fw_cfg->max_ppl_count - 1, GFP_KERNEL);
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if (id < 0)
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return id;
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ret = avs_ipc_create_pipeline(adev, req_size, priority, id, lp, attributes);
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if (ret) {
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ida_free(&adev->ppl_ida, id);
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return AVS_IPC_RET(ret);
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}
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*instance_id = id;
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return 0;
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}
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int avs_dsp_delete_pipeline(struct avs_dev *adev, u8 instance_id)
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{
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int ret;
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ret = avs_ipc_delete_pipeline(adev, instance_id);
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if (ret)
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ret = AVS_IPC_RET(ret);
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ida_free(&adev->ppl_ida, instance_id);
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return ret;
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}
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