99 lines
2.2 KiB
C
99 lines
2.2 KiB
C
/* SPDX-License-Identifier: GPL-2.0+ */
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/*
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* AMD ALSA SoC PDM Driver
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*
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* Copyright (C) 2022 Advanced Micro Devices, Inc. All rights reserved.
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*/
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#include <sound/acp63_chip_offset_byte.h>
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#define ACP_DEVICE_ID 0x15E2
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#define ACP6x_REG_START 0x1240000
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#define ACP6x_REG_END 0x1250200
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#define ACP6x_DEVS 3
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#define ACP6x_PDM_MODE 1
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#define ACP_SOFT_RESET_SOFTRESET_AUDDONE_MASK 0x00010001
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#define ACP_PGFSM_CNTL_POWER_ON_MASK 1
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#define ACP_PGFSM_CNTL_POWER_OFF_MASK 0
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#define ACP_PGFSM_STATUS_MASK 3
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#define ACP_POWERED_ON 0
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#define ACP_POWER_ON_IN_PROGRESS 1
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#define ACP_POWERED_OFF 2
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#define ACP_POWER_OFF_IN_PROGRESS 3
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#define ACP_ERROR_MASK 0x20000000
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#define ACP_EXT_INTR_STAT_CLEAR_MASK 0xFFFFFFFF
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#define PDM_DMA_STAT 0x10
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#define PDM_DMA_INTR_MASK 0x10000
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#define ACP_ERROR_STAT 29
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#define PDM_DECIMATION_FACTOR 2
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#define ACP_PDM_CLK_FREQ_MASK 7
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#define ACP_WOV_MISC_CTRL_MASK 0x10
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#define ACP_PDM_ENABLE 1
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#define ACP_PDM_DISABLE 0
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#define ACP_PDM_DMA_EN_STATUS 2
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#define TWO_CH 2
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#define DELAY_US 5
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#define ACP_COUNTER 20000
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#define ACP_SRAM_PTE_OFFSET 0x03800000
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#define PAGE_SIZE_4K_ENABLE 2
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#define PDM_PTE_OFFSET 0
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#define PDM_MEM_WINDOW_START 0x4000000
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#define CAPTURE_MIN_NUM_PERIODS 4
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#define CAPTURE_MAX_NUM_PERIODS 4
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#define CAPTURE_MAX_PERIOD_SIZE 8192
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#define CAPTURE_MIN_PERIOD_SIZE 4096
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#define MAX_BUFFER (CAPTURE_MAX_PERIOD_SIZE * CAPTURE_MAX_NUM_PERIODS)
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#define MIN_BUFFER MAX_BUFFER
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/* time in ms for runtime suspend delay */
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#define ACP_SUSPEND_DELAY_MS 2000
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enum acp_config {
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ACP_CONFIG_0 = 0,
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ACP_CONFIG_1,
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ACP_CONFIG_2,
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ACP_CONFIG_3,
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ACP_CONFIG_4,
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ACP_CONFIG_5,
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ACP_CONFIG_6,
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ACP_CONFIG_7,
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ACP_CONFIG_8,
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ACP_CONFIG_9,
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ACP_CONFIG_10,
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ACP_CONFIG_11,
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ACP_CONFIG_12,
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ACP_CONFIG_13,
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ACP_CONFIG_14,
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ACP_CONFIG_15,
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};
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struct pdm_stream_instance {
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u16 num_pages;
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u16 channels;
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dma_addr_t dma_addr;
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u64 bytescount;
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void __iomem *acp63_base;
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};
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struct pdm_dev_data {
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u32 pdm_irq;
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void __iomem *acp63_base;
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struct snd_pcm_substream *capture_stream;
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};
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static inline u32 acp63_readl(void __iomem *base_addr)
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{
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return readl(base_addr);
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}
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static inline void acp63_writel(u32 val, void __iomem *base_addr)
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{
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writel(val, base_addr);
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}
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