560 lines
15 KiB
C
560 lines
15 KiB
C
// SPDX-License-Identifier: (GPL-2.0-only OR BSD-3-Clause)
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//
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// This file is provided under a dual BSD/GPLv2 license. When using or
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// redistributing this file, you may do so under either license.
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//
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// Copyright(c) 2021 Advanced Micro Devices, Inc.
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//
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// Authors: Ajit Kumar Pandey <AjitKumar.Pandey@amd.com>
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//
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/*
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* Generic Hardware interface for ACP Audio I2S controller
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*/
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#include <linux/platform_device.h>
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#include <linux/module.h>
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#include <linux/err.h>
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#include <linux/io.h>
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#include <sound/pcm_params.h>
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#include <sound/soc.h>
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#include <sound/soc-dai.h>
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#include <linux/dma-mapping.h>
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#include "amd.h"
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#define DRV_NAME "acp_i2s_playcap"
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static int acp_i2s_set_fmt(struct snd_soc_dai *cpu_dai,
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unsigned int fmt)
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{
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struct acp_dev_data *adata = snd_soc_dai_get_drvdata(cpu_dai);
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int mode;
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mode = fmt & SND_SOC_DAIFMT_FORMAT_MASK;
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switch (mode) {
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case SND_SOC_DAIFMT_I2S:
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adata->tdm_mode = TDM_DISABLE;
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break;
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case SND_SOC_DAIFMT_DSP_A:
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adata->tdm_mode = TDM_ENABLE;
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break;
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default:
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return -EINVAL;
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}
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return 0;
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}
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static int acp_i2s_set_tdm_slot(struct snd_soc_dai *dai, u32 tx_mask, u32 rx_mask,
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int slots, int slot_width)
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{
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struct device *dev = dai->component->dev;
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struct acp_dev_data *adata = snd_soc_dai_get_drvdata(dai);
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struct acp_stream *stream;
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int slot_len;
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switch (slot_width) {
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case SLOT_WIDTH_8:
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slot_len = 8;
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break;
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case SLOT_WIDTH_16:
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slot_len = 16;
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break;
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case SLOT_WIDTH_24:
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slot_len = 24;
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break;
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case SLOT_WIDTH_32:
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slot_len = 0;
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break;
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default:
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dev_err(dev, "Unsupported bitdepth %d\n", slot_width);
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return -EINVAL;
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}
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spin_lock_irq(&adata->acp_lock);
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list_for_each_entry(stream, &adata->stream_list, list) {
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if (tx_mask && stream->dir == SNDRV_PCM_STREAM_PLAYBACK)
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adata->tdm_tx_fmt[stream->dai_id - 1] =
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FRM_LEN | (slots << 15) | (slot_len << 18);
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else if (rx_mask && stream->dir == SNDRV_PCM_STREAM_CAPTURE)
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adata->tdm_rx_fmt[stream->dai_id - 1] =
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FRM_LEN | (slots << 15) | (slot_len << 18);
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}
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spin_unlock_irq(&adata->acp_lock);
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return 0;
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}
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static int acp_i2s_hwparams(struct snd_pcm_substream *substream, struct snd_pcm_hw_params *params,
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struct snd_soc_dai *dai)
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{
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struct device *dev = dai->component->dev;
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struct acp_dev_data *adata;
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struct acp_resource *rsrc;
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u32 val;
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u32 xfer_resolution;
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u32 reg_val, fmt_reg, tdm_fmt;
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u32 lrclk_div_val, bclk_div_val;
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adata = snd_soc_dai_get_drvdata(dai);
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rsrc = adata->rsrc;
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/* These values are as per Hardware Spec */
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switch (params_format(params)) {
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case SNDRV_PCM_FORMAT_U8:
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case SNDRV_PCM_FORMAT_S8:
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xfer_resolution = 0x0;
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break;
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case SNDRV_PCM_FORMAT_S16_LE:
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xfer_resolution = 0x02;
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break;
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case SNDRV_PCM_FORMAT_S24_LE:
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xfer_resolution = 0x04;
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break;
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case SNDRV_PCM_FORMAT_S32_LE:
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xfer_resolution = 0x05;
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break;
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default:
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return -EINVAL;
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}
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if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
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switch (dai->driver->id) {
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case I2S_BT_INSTANCE:
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reg_val = ACP_BTTDM_ITER;
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fmt_reg = ACP_BTTDM_TXFRMT;
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break;
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case I2S_SP_INSTANCE:
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reg_val = ACP_I2STDM_ITER;
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fmt_reg = ACP_I2STDM_TXFRMT;
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break;
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case I2S_HS_INSTANCE:
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reg_val = ACP_HSTDM_ITER;
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fmt_reg = ACP_HSTDM_TXFRMT;
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break;
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default:
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dev_err(dev, "Invalid dai id %x\n", dai->driver->id);
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return -EINVAL;
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}
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} else {
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switch (dai->driver->id) {
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case I2S_BT_INSTANCE:
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reg_val = ACP_BTTDM_IRER;
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fmt_reg = ACP_BTTDM_RXFRMT;
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break;
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case I2S_SP_INSTANCE:
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reg_val = ACP_I2STDM_IRER;
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fmt_reg = ACP_I2STDM_RXFRMT;
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break;
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case I2S_HS_INSTANCE:
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reg_val = ACP_HSTDM_IRER;
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fmt_reg = ACP_HSTDM_RXFRMT;
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break;
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default:
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dev_err(dev, "Invalid dai id %x\n", dai->driver->id);
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return -EINVAL;
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}
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}
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val = readl(adata->acp_base + reg_val);
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val &= ~ACP3x_ITER_IRER_SAMP_LEN_MASK;
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val = val | (xfer_resolution << 3);
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writel(val, adata->acp_base + reg_val);
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if (adata->tdm_mode) {
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val = readl(adata->acp_base + reg_val);
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writel(val | BIT(1), adata->acp_base + reg_val);
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if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
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tdm_fmt = adata->tdm_tx_fmt[dai->driver->id - 1];
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else
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tdm_fmt = adata->tdm_rx_fmt[dai->driver->id - 1];
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writel(tdm_fmt, adata->acp_base + fmt_reg);
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}
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if (rsrc->soc_mclk) {
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switch (params_format(params)) {
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case SNDRV_PCM_FORMAT_S16_LE:
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switch (params_rate(params)) {
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case 8000:
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bclk_div_val = 768;
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break;
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case 16000:
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bclk_div_val = 384;
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break;
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case 24000:
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bclk_div_val = 256;
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break;
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case 32000:
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bclk_div_val = 192;
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break;
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case 44100:
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case 48000:
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bclk_div_val = 128;
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break;
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case 88200:
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case 96000:
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bclk_div_val = 64;
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break;
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case 192000:
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bclk_div_val = 32;
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break;
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default:
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return -EINVAL;
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}
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lrclk_div_val = 32;
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break;
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case SNDRV_PCM_FORMAT_S32_LE:
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switch (params_rate(params)) {
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case 8000:
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bclk_div_val = 384;
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break;
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case 16000:
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bclk_div_val = 192;
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break;
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case 24000:
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bclk_div_val = 128;
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break;
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case 32000:
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bclk_div_val = 96;
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break;
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case 44100:
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case 48000:
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bclk_div_val = 64;
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break;
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case 88200:
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case 96000:
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bclk_div_val = 32;
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break;
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case 192000:
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bclk_div_val = 16;
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break;
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default:
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return -EINVAL;
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}
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lrclk_div_val = 64;
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break;
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default:
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return -EINVAL;
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}
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adata->lrclk_div = lrclk_div_val;
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adata->bclk_div = bclk_div_val;
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}
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return 0;
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}
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static int acp_i2s_trigger(struct snd_pcm_substream *substream, int cmd, struct snd_soc_dai *dai)
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{
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struct acp_stream *stream = substream->runtime->private_data;
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struct device *dev = dai->component->dev;
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struct acp_dev_data *adata = dev_get_drvdata(dev);
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struct acp_resource *rsrc = adata->rsrc;
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u32 val, period_bytes, reg_val, ier_val, water_val, buf_size, buf_reg;
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period_bytes = frames_to_bytes(substream->runtime, substream->runtime->period_size);
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buf_size = frames_to_bytes(substream->runtime, substream->runtime->buffer_size);
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switch (cmd) {
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case SNDRV_PCM_TRIGGER_START:
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case SNDRV_PCM_TRIGGER_RESUME:
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case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
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stream->bytescount = acp_get_byte_count(adata, stream->dai_id, substream->stream);
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if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
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switch (dai->driver->id) {
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case I2S_BT_INSTANCE:
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water_val = ACP_BT_TX_INTR_WATERMARK_SIZE;
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reg_val = ACP_BTTDM_ITER;
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ier_val = ACP_BTTDM_IER;
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buf_reg = ACP_BT_TX_RINGBUFSIZE;
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break;
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case I2S_SP_INSTANCE:
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water_val = ACP_I2S_TX_INTR_WATERMARK_SIZE;
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reg_val = ACP_I2STDM_ITER;
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ier_val = ACP_I2STDM_IER;
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buf_reg = ACP_I2S_TX_RINGBUFSIZE;
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break;
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case I2S_HS_INSTANCE:
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water_val = ACP_HS_TX_INTR_WATERMARK_SIZE;
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reg_val = ACP_HSTDM_ITER;
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ier_val = ACP_HSTDM_IER;
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buf_reg = ACP_HS_TX_RINGBUFSIZE;
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break;
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default:
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dev_err(dev, "Invalid dai id %x\n", dai->driver->id);
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return -EINVAL;
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}
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} else {
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switch (dai->driver->id) {
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case I2S_BT_INSTANCE:
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water_val = ACP_BT_RX_INTR_WATERMARK_SIZE;
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reg_val = ACP_BTTDM_IRER;
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ier_val = ACP_BTTDM_IER;
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buf_reg = ACP_BT_RX_RINGBUFSIZE;
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break;
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case I2S_SP_INSTANCE:
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water_val = ACP_I2S_RX_INTR_WATERMARK_SIZE;
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reg_val = ACP_I2STDM_IRER;
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ier_val = ACP_I2STDM_IER;
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buf_reg = ACP_I2S_RX_RINGBUFSIZE;
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break;
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case I2S_HS_INSTANCE:
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water_val = ACP_HS_RX_INTR_WATERMARK_SIZE;
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reg_val = ACP_HSTDM_IRER;
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ier_val = ACP_HSTDM_IER;
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buf_reg = ACP_HS_RX_RINGBUFSIZE;
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break;
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default:
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dev_err(dev, "Invalid dai id %x\n", dai->driver->id);
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return -EINVAL;
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}
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}
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writel(period_bytes, adata->acp_base + water_val);
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writel(buf_size, adata->acp_base + buf_reg);
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val = readl(adata->acp_base + reg_val);
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val = val | BIT(0);
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writel(val, adata->acp_base + reg_val);
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writel(1, adata->acp_base + ier_val);
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if (rsrc->soc_mclk)
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acp_set_i2s_clk(adata, dai->driver->id);
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return 0;
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case SNDRV_PCM_TRIGGER_STOP:
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case SNDRV_PCM_TRIGGER_SUSPEND:
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case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
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if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
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switch (dai->driver->id) {
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case I2S_BT_INSTANCE:
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reg_val = ACP_BTTDM_ITER;
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break;
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case I2S_SP_INSTANCE:
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reg_val = ACP_I2STDM_ITER;
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break;
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case I2S_HS_INSTANCE:
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reg_val = ACP_HSTDM_ITER;
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break;
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default:
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dev_err(dev, "Invalid dai id %x\n", dai->driver->id);
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return -EINVAL;
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}
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} else {
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switch (dai->driver->id) {
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case I2S_BT_INSTANCE:
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reg_val = ACP_BTTDM_IRER;
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break;
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case I2S_SP_INSTANCE:
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reg_val = ACP_I2STDM_IRER;
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break;
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case I2S_HS_INSTANCE:
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reg_val = ACP_HSTDM_IRER;
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break;
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default:
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dev_err(dev, "Invalid dai id %x\n", dai->driver->id);
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return -EINVAL;
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}
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}
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val = readl(adata->acp_base + reg_val);
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val = val & ~BIT(0);
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writel(val, adata->acp_base + reg_val);
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if (!(readl(adata->acp_base + ACP_BTTDM_ITER) & BIT(0)) &&
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!(readl(adata->acp_base + ACP_BTTDM_IRER) & BIT(0)))
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writel(0, adata->acp_base + ACP_BTTDM_IER);
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if (!(readl(adata->acp_base + ACP_I2STDM_ITER) & BIT(0)) &&
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!(readl(adata->acp_base + ACP_I2STDM_IRER) & BIT(0)))
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writel(0, adata->acp_base + ACP_I2STDM_IER);
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if (!(readl(adata->acp_base + ACP_HSTDM_ITER) & BIT(0)) &&
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!(readl(adata->acp_base + ACP_HSTDM_IRER) & BIT(0)))
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writel(0, adata->acp_base + ACP_HSTDM_IER);
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return 0;
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default:
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return -EINVAL;
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}
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return 0;
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}
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static int acp_i2s_prepare(struct snd_pcm_substream *substream, struct snd_soc_dai *dai)
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{
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struct device *dev = dai->component->dev;
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struct acp_dev_data *adata = dev_get_drvdata(dev);
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struct acp_resource *rsrc = adata->rsrc;
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struct acp_stream *stream = substream->runtime->private_data;
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u32 reg_dma_size = 0, reg_fifo_size = 0, reg_fifo_addr = 0;
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u32 phy_addr = 0, acp_fifo_addr = 0, ext_int_ctrl;
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unsigned int dir = substream->stream;
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switch (dai->driver->id) {
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case I2S_SP_INSTANCE:
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if (dir == SNDRV_PCM_STREAM_PLAYBACK) {
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reg_dma_size = ACP_I2S_TX_DMA_SIZE;
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acp_fifo_addr = rsrc->sram_pte_offset +
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SP_PB_FIFO_ADDR_OFFSET;
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reg_fifo_addr = ACP_I2S_TX_FIFOADDR;
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reg_fifo_size = ACP_I2S_TX_FIFOSIZE;
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phy_addr = I2S_SP_TX_MEM_WINDOW_START + stream->reg_offset;
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writel(phy_addr, adata->acp_base + ACP_I2S_TX_RINGBUFADDR);
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} else {
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reg_dma_size = ACP_I2S_RX_DMA_SIZE;
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acp_fifo_addr = rsrc->sram_pte_offset +
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SP_CAPT_FIFO_ADDR_OFFSET;
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reg_fifo_addr = ACP_I2S_RX_FIFOADDR;
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reg_fifo_size = ACP_I2S_RX_FIFOSIZE;
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phy_addr = I2S_SP_RX_MEM_WINDOW_START + stream->reg_offset;
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writel(phy_addr, adata->acp_base + ACP_I2S_RX_RINGBUFADDR);
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}
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break;
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case I2S_BT_INSTANCE:
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if (dir == SNDRV_PCM_STREAM_PLAYBACK) {
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reg_dma_size = ACP_BT_TX_DMA_SIZE;
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acp_fifo_addr = rsrc->sram_pte_offset +
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BT_PB_FIFO_ADDR_OFFSET;
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reg_fifo_addr = ACP_BT_TX_FIFOADDR;
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reg_fifo_size = ACP_BT_TX_FIFOSIZE;
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phy_addr = I2S_BT_TX_MEM_WINDOW_START + stream->reg_offset;
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writel(phy_addr, adata->acp_base + ACP_BT_TX_RINGBUFADDR);
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} else {
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reg_dma_size = ACP_BT_RX_DMA_SIZE;
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acp_fifo_addr = rsrc->sram_pte_offset +
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BT_CAPT_FIFO_ADDR_OFFSET;
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reg_fifo_addr = ACP_BT_RX_FIFOADDR;
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reg_fifo_size = ACP_BT_RX_FIFOSIZE;
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phy_addr = I2S_BT_TX_MEM_WINDOW_START + stream->reg_offset;
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writel(phy_addr, adata->acp_base + ACP_BT_RX_RINGBUFADDR);
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}
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break;
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case I2S_HS_INSTANCE:
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if (dir == SNDRV_PCM_STREAM_PLAYBACK) {
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reg_dma_size = ACP_HS_TX_DMA_SIZE;
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acp_fifo_addr = rsrc->sram_pte_offset +
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HS_PB_FIFO_ADDR_OFFSET;
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reg_fifo_addr = ACP_HS_TX_FIFOADDR;
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reg_fifo_size = ACP_HS_TX_FIFOSIZE;
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phy_addr = I2S_HS_TX_MEM_WINDOW_START + stream->reg_offset;
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writel(phy_addr, adata->acp_base + ACP_HS_TX_RINGBUFADDR);
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} else {
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reg_dma_size = ACP_HS_RX_DMA_SIZE;
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acp_fifo_addr = rsrc->sram_pte_offset +
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HS_CAPT_FIFO_ADDR_OFFSET;
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reg_fifo_addr = ACP_HS_RX_FIFOADDR;
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reg_fifo_size = ACP_HS_RX_FIFOSIZE;
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phy_addr = I2S_HS_RX_MEM_WINDOW_START + stream->reg_offset;
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writel(phy_addr, adata->acp_base + ACP_HS_RX_RINGBUFADDR);
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}
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break;
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default:
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dev_err(dev, "Invalid dai id %x\n", dai->driver->id);
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return -EINVAL;
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}
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writel(DMA_SIZE, adata->acp_base + reg_dma_size);
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writel(acp_fifo_addr, adata->acp_base + reg_fifo_addr);
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writel(FIFO_SIZE, adata->acp_base + reg_fifo_size);
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ext_int_ctrl = readl(ACP_EXTERNAL_INTR_CNTL(adata, rsrc->irqp_used));
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ext_int_ctrl |= BIT(I2S_RX_THRESHOLD(rsrc->offset)) |
|
|
BIT(BT_RX_THRESHOLD(rsrc->offset)) |
|
|
BIT(I2S_TX_THRESHOLD(rsrc->offset)) |
|
|
BIT(BT_TX_THRESHOLD(rsrc->offset)) |
|
|
BIT(HS_RX_THRESHOLD(rsrc->offset)) |
|
|
BIT(HS_TX_THRESHOLD(rsrc->offset));
|
|
|
|
writel(ext_int_ctrl, ACP_EXTERNAL_INTR_CNTL(adata, rsrc->irqp_used));
|
|
|
|
return 0;
|
|
}
|
|
|
|
static int acp_i2s_startup(struct snd_pcm_substream *substream, struct snd_soc_dai *dai)
|
|
{
|
|
struct acp_stream *stream = substream->runtime->private_data;
|
|
struct device *dev = dai->component->dev;
|
|
struct acp_dev_data *adata = dev_get_drvdata(dev);
|
|
struct acp_resource *rsrc = adata->rsrc;
|
|
unsigned int dir = substream->stream;
|
|
unsigned int irq_bit = 0;
|
|
|
|
switch (dai->driver->id) {
|
|
case I2S_SP_INSTANCE:
|
|
if (dir == SNDRV_PCM_STREAM_PLAYBACK) {
|
|
irq_bit = BIT(I2S_TX_THRESHOLD(rsrc->offset));
|
|
stream->pte_offset = ACP_SRAM_SP_PB_PTE_OFFSET;
|
|
stream->fifo_offset = SP_PB_FIFO_ADDR_OFFSET;
|
|
} else {
|
|
irq_bit = BIT(I2S_RX_THRESHOLD(rsrc->offset));
|
|
stream->pte_offset = ACP_SRAM_SP_CP_PTE_OFFSET;
|
|
stream->fifo_offset = SP_CAPT_FIFO_ADDR_OFFSET;
|
|
}
|
|
break;
|
|
case I2S_BT_INSTANCE:
|
|
if (dir == SNDRV_PCM_STREAM_PLAYBACK) {
|
|
irq_bit = BIT(BT_TX_THRESHOLD(rsrc->offset));
|
|
stream->pte_offset = ACP_SRAM_BT_PB_PTE_OFFSET;
|
|
stream->fifo_offset = BT_PB_FIFO_ADDR_OFFSET;
|
|
} else {
|
|
irq_bit = BIT(BT_RX_THRESHOLD(rsrc->offset));
|
|
stream->pte_offset = ACP_SRAM_BT_CP_PTE_OFFSET;
|
|
stream->fifo_offset = BT_CAPT_FIFO_ADDR_OFFSET;
|
|
}
|
|
break;
|
|
case I2S_HS_INSTANCE:
|
|
if (dir == SNDRV_PCM_STREAM_PLAYBACK) {
|
|
irq_bit = BIT(HS_TX_THRESHOLD(rsrc->offset));
|
|
stream->pte_offset = ACP_SRAM_HS_PB_PTE_OFFSET;
|
|
stream->fifo_offset = HS_PB_FIFO_ADDR_OFFSET;
|
|
} else {
|
|
irq_bit = BIT(HS_RX_THRESHOLD(rsrc->offset));
|
|
stream->pte_offset = ACP_SRAM_HS_CP_PTE_OFFSET;
|
|
stream->fifo_offset = HS_CAPT_FIFO_ADDR_OFFSET;
|
|
}
|
|
break;
|
|
default:
|
|
dev_err(dev, "Invalid dai id %x\n", dai->driver->id);
|
|
return -EINVAL;
|
|
}
|
|
|
|
/* Save runtime dai configuration in stream */
|
|
stream->id = dai->driver->id + dir;
|
|
stream->dai_id = dai->driver->id;
|
|
stream->irq_bit = irq_bit;
|
|
stream->dir = substream->stream;
|
|
|
|
return 0;
|
|
}
|
|
|
|
const struct snd_soc_dai_ops asoc_acp_cpu_dai_ops = {
|
|
.startup = acp_i2s_startup,
|
|
.hw_params = acp_i2s_hwparams,
|
|
.prepare = acp_i2s_prepare,
|
|
.trigger = acp_i2s_trigger,
|
|
.set_fmt = acp_i2s_set_fmt,
|
|
.set_tdm_slot = acp_i2s_set_tdm_slot,
|
|
};
|
|
EXPORT_SYMBOL_NS_GPL(asoc_acp_cpu_dai_ops, SND_SOC_ACP_COMMON);
|
|
|
|
int asoc_acp_i2s_probe(struct snd_soc_dai *dai)
|
|
{
|
|
struct device *dev = dai->component->dev;
|
|
struct acp_dev_data *adata = dev_get_drvdata(dev);
|
|
struct acp_resource *rsrc = adata->rsrc;
|
|
unsigned int val;
|
|
|
|
if (!adata->acp_base) {
|
|
dev_err(dev, "I2S base is NULL\n");
|
|
return -EINVAL;
|
|
}
|
|
|
|
val = readl(adata->acp_base + rsrc->i2s_pin_cfg_offset);
|
|
if (val != rsrc->i2s_mode) {
|
|
dev_err(dev, "I2S Mode not supported val %x\n", val);
|
|
return -EINVAL;
|
|
}
|
|
|
|
return 0;
|
|
}
|
|
EXPORT_SYMBOL_NS_GPL(asoc_acp_i2s_probe, SND_SOC_ACP_COMMON);
|
|
|
|
MODULE_LICENSE("Dual BSD/GPL");
|
|
MODULE_ALIAS(DRV_NAME);
|