119 lines
3.5 KiB
C
119 lines
3.5 KiB
C
// SPDX-License-Identifier: GPL-2.0
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/*
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* Thunderbolt driver - quirks
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*
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* Copyright (c) 2020 Mario Limonciello <mario.limonciello@dell.com>
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*/
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#include "tb.h"
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static void quirk_force_power_link(struct tb_switch *sw)
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{
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sw->quirks |= QUIRK_FORCE_POWER_LINK_CONTROLLER;
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}
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static void quirk_dp_credit_allocation(struct tb_switch *sw)
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{
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if (sw->credit_allocation && sw->min_dp_main_credits == 56) {
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sw->min_dp_main_credits = 18;
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tb_sw_dbg(sw, "quirked DP main: %u\n", sw->min_dp_main_credits);
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}
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}
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static void quirk_clx_disable(struct tb_switch *sw)
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{
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sw->quirks |= QUIRK_NO_CLX;
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tb_sw_dbg(sw, "disabling CL states\n");
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}
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static void quirk_usb3_maximum_bandwidth(struct tb_switch *sw)
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{
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struct tb_port *port;
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tb_switch_for_each_port(sw, port) {
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if (!tb_port_is_usb3_down(port))
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continue;
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port->max_bw = 16376;
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tb_port_dbg(port, "USB3 maximum bandwidth limited to %u Mb/s\n",
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port->max_bw);
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}
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}
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struct tb_quirk {
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u16 hw_vendor_id;
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u16 hw_device_id;
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u16 vendor;
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u16 device;
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void (*hook)(struct tb_switch *sw);
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};
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static const struct tb_quirk tb_quirks[] = {
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/* Dell WD19TB supports self-authentication on unplug */
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{ 0x0000, 0x0000, 0x00d4, 0xb070, quirk_force_power_link },
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{ 0x0000, 0x0000, 0x00d4, 0xb071, quirk_force_power_link },
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/*
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* Intel Goshen Ridge NVM 27 and before report wrong number of
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* DP buffers.
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*/
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{ 0x8087, 0x0b26, 0x0000, 0x0000, quirk_dp_credit_allocation },
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/*
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* Limit the maximum USB3 bandwidth for the following Intel USB4
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* host routers due to a hardware issue.
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*/
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{ 0x8087, PCI_DEVICE_ID_INTEL_ADL_NHI0, 0x0000, 0x0000,
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quirk_usb3_maximum_bandwidth },
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{ 0x8087, PCI_DEVICE_ID_INTEL_ADL_NHI1, 0x0000, 0x0000,
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quirk_usb3_maximum_bandwidth },
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{ 0x8087, PCI_DEVICE_ID_INTEL_RPL_NHI0, 0x0000, 0x0000,
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quirk_usb3_maximum_bandwidth },
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{ 0x8087, PCI_DEVICE_ID_INTEL_RPL_NHI1, 0x0000, 0x0000,
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quirk_usb3_maximum_bandwidth },
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{ 0x8087, PCI_DEVICE_ID_INTEL_MTL_M_NHI0, 0x0000, 0x0000,
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quirk_usb3_maximum_bandwidth },
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{ 0x8087, PCI_DEVICE_ID_INTEL_MTL_P_NHI0, 0x0000, 0x0000,
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quirk_usb3_maximum_bandwidth },
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{ 0x8087, PCI_DEVICE_ID_INTEL_MTL_P_NHI1, 0x0000, 0x0000,
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quirk_usb3_maximum_bandwidth },
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{ 0x8087, PCI_DEVICE_ID_INTEL_BARLOW_RIDGE_HOST_80G_NHI, 0x0000, 0x0000,
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quirk_usb3_maximum_bandwidth },
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{ 0x8087, PCI_DEVICE_ID_INTEL_BARLOW_RIDGE_HOST_40G_NHI, 0x0000, 0x0000,
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quirk_usb3_maximum_bandwidth },
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{ 0x8087, PCI_DEVICE_ID_INTEL_BARLOW_RIDGE_HUB_80G_BRIDGE, 0x0000, 0x0000,
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quirk_usb3_maximum_bandwidth },
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{ 0x8087, PCI_DEVICE_ID_INTEL_BARLOW_RIDGE_HUB_40G_BRIDGE, 0x0000, 0x0000,
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quirk_usb3_maximum_bandwidth },
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/*
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* CLx is not supported on AMD USB4 Yellow Carp and Pink Sardine platforms.
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*/
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{ 0x0438, 0x0208, 0x0000, 0x0000, quirk_clx_disable },
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{ 0x0438, 0x0209, 0x0000, 0x0000, quirk_clx_disable },
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{ 0x0438, 0x020a, 0x0000, 0x0000, quirk_clx_disable },
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{ 0x0438, 0x020b, 0x0000, 0x0000, quirk_clx_disable },
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};
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/**
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* tb_check_quirks() - Check for quirks to apply
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* @sw: Thunderbolt switch
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*
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* Apply any quirks for the Thunderbolt controller.
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*/
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void tb_check_quirks(struct tb_switch *sw)
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{
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int i;
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for (i = 0; i < ARRAY_SIZE(tb_quirks); i++) {
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const struct tb_quirk *q = &tb_quirks[i];
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if (q->hw_vendor_id && q->hw_vendor_id != sw->config.vendor_id)
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continue;
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if (q->hw_device_id && q->hw_device_id != sw->config.device_id)
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continue;
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if (q->vendor && q->vendor != sw->vendor)
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continue;
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if (q->device && q->device != sw->device)
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continue;
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q->hook(sw);
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}
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}
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