263 lines
6.8 KiB
C
263 lines
6.8 KiB
C
// SPDX-License-Identifier: GPL-2.0-only
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/*
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* Copyright (c) 2021, MediaTek Inc.
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* Copyright (c) 2021-2022, Intel Corporation.
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*
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* Authors:
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* Haijun Liu <haijun.liu@mediatek.com>
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* Moises Veleta <moises.veleta@intel.com>
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* Sreehari Kancharla <sreehari.kancharla@intel.com>
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*
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* Contributors:
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* Amir Hanania <amir.hanania@intel.com>
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* Chiranjeevi Rapolu <chiranjeevi.rapolu@intel.com>
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* Ricardo Martinez <ricardo.martinez@linux.intel.com>
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*/
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#include <linux/bits.h>
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#include <linux/bitops.h>
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#include <linux/device.h>
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#include <linux/io-64-nonatomic-lo-hi.h>
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#include <linux/pci.h>
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#include <linux/string.h>
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#include <linux/types.h>
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#include "t7xx_pci.h"
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#include "t7xx_pcie_mac.h"
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#include "t7xx_reg.h"
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#define T7XX_PCIE_REG_BAR 2
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#define T7XX_PCIE_REG_PORT ATR_SRC_PCI_WIN0
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#define T7XX_PCIE_REG_TABLE_NUM 0
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#define T7XX_PCIE_REG_TRSL_PORT ATR_DST_AXIM_0
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#define T7XX_PCIE_DEV_DMA_PORT_START ATR_SRC_AXIS_0
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#define T7XX_PCIE_DEV_DMA_PORT_END ATR_SRC_AXIS_2
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#define T7XX_PCIE_DEV_DMA_TABLE_NUM 0
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#define T7XX_PCIE_DEV_DMA_TRSL_ADDR 0
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#define T7XX_PCIE_DEV_DMA_SRC_ADDR 0
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#define T7XX_PCIE_DEV_DMA_TRANSPARENT 1
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#define T7XX_PCIE_DEV_DMA_SIZE 0
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enum t7xx_atr_src_port {
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ATR_SRC_PCI_WIN0,
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ATR_SRC_PCI_WIN1,
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ATR_SRC_AXIS_0,
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ATR_SRC_AXIS_1,
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ATR_SRC_AXIS_2,
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ATR_SRC_AXIS_3,
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};
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enum t7xx_atr_dst_port {
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ATR_DST_PCI_TRX,
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ATR_DST_PCI_CONFIG,
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ATR_DST_AXIM_0 = 4,
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ATR_DST_AXIM_1,
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ATR_DST_AXIM_2,
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ATR_DST_AXIM_3,
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};
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struct t7xx_atr_config {
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u64 src_addr;
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u64 trsl_addr;
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u64 size;
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u32 port;
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u32 table;
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enum t7xx_atr_dst_port trsl_id;
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u32 transparent;
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};
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static void t7xx_pcie_mac_atr_tables_dis(void __iomem *pbase, enum t7xx_atr_src_port port)
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{
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void __iomem *reg;
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int i, offset;
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for (i = 0; i < ATR_TABLE_NUM_PER_ATR; i++) {
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offset = ATR_PORT_OFFSET * port + ATR_TABLE_OFFSET * i;
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reg = pbase + ATR_PCIE_WIN0_T0_ATR_PARAM_SRC_ADDR + offset;
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iowrite64(0, reg);
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}
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}
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static int t7xx_pcie_mac_atr_cfg(struct t7xx_pci_dev *t7xx_dev, struct t7xx_atr_config *cfg)
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{
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struct device *dev = &t7xx_dev->pdev->dev;
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void __iomem *pbase = IREG_BASE(t7xx_dev);
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int atr_size, pos, offset;
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void __iomem *reg;
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u64 value;
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if (cfg->transparent) {
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/* No address conversion is performed */
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atr_size = ATR_TRANSPARENT_SIZE;
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} else {
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if (cfg->src_addr & (cfg->size - 1)) {
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dev_err(dev, "Source address is not aligned to size\n");
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return -EINVAL;
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}
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if (cfg->trsl_addr & (cfg->size - 1)) {
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dev_err(dev, "Translation address %llx is not aligned to size %llx\n",
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cfg->trsl_addr, cfg->size - 1);
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return -EINVAL;
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}
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pos = __ffs64(cfg->size);
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/* HW calculates the address translation space as 2^(atr_size + 1) */
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atr_size = pos - 1;
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}
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offset = ATR_PORT_OFFSET * cfg->port + ATR_TABLE_OFFSET * cfg->table;
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reg = pbase + ATR_PCIE_WIN0_T0_TRSL_ADDR + offset;
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value = cfg->trsl_addr & ATR_PCIE_WIN0_ADDR_ALGMT;
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iowrite64(value, reg);
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reg = pbase + ATR_PCIE_WIN0_T0_TRSL_PARAM + offset;
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iowrite32(cfg->trsl_id, reg);
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reg = pbase + ATR_PCIE_WIN0_T0_ATR_PARAM_SRC_ADDR + offset;
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value = (cfg->src_addr & ATR_PCIE_WIN0_ADDR_ALGMT) | (atr_size << 1) | BIT(0);
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iowrite64(value, reg);
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/* Ensure ATR is set */
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ioread64(reg);
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return 0;
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}
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/**
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* t7xx_pcie_mac_atr_init() - Initialize address translation.
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* @t7xx_dev: MTK device.
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*
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* Setup ATR for ports & device.
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*/
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void t7xx_pcie_mac_atr_init(struct t7xx_pci_dev *t7xx_dev)
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{
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struct t7xx_atr_config cfg;
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u32 i;
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/* Disable for all ports */
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for (i = ATR_SRC_PCI_WIN0; i <= ATR_SRC_AXIS_3; i++)
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t7xx_pcie_mac_atr_tables_dis(IREG_BASE(t7xx_dev), i);
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memset(&cfg, 0, sizeof(cfg));
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/* Config ATR for RC to access device's register */
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cfg.src_addr = pci_resource_start(t7xx_dev->pdev, T7XX_PCIE_REG_BAR);
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cfg.size = T7XX_PCIE_REG_SIZE_CHIP;
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cfg.trsl_addr = T7XX_PCIE_REG_TRSL_ADDR_CHIP;
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cfg.port = T7XX_PCIE_REG_PORT;
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cfg.table = T7XX_PCIE_REG_TABLE_NUM;
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cfg.trsl_id = T7XX_PCIE_REG_TRSL_PORT;
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t7xx_pcie_mac_atr_tables_dis(IREG_BASE(t7xx_dev), cfg.port);
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t7xx_pcie_mac_atr_cfg(t7xx_dev, &cfg);
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t7xx_dev->base_addr.pcie_dev_reg_trsl_addr = T7XX_PCIE_REG_TRSL_ADDR_CHIP;
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/* Config ATR for EP to access RC's memory */
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for (i = T7XX_PCIE_DEV_DMA_PORT_START; i <= T7XX_PCIE_DEV_DMA_PORT_END; i++) {
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cfg.src_addr = T7XX_PCIE_DEV_DMA_SRC_ADDR;
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cfg.size = T7XX_PCIE_DEV_DMA_SIZE;
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cfg.trsl_addr = T7XX_PCIE_DEV_DMA_TRSL_ADDR;
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cfg.port = i;
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cfg.table = T7XX_PCIE_DEV_DMA_TABLE_NUM;
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cfg.trsl_id = ATR_DST_PCI_TRX;
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cfg.transparent = T7XX_PCIE_DEV_DMA_TRANSPARENT;
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t7xx_pcie_mac_atr_tables_dis(IREG_BASE(t7xx_dev), cfg.port);
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t7xx_pcie_mac_atr_cfg(t7xx_dev, &cfg);
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}
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}
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/**
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* t7xx_pcie_mac_enable_disable_int() - Enable/disable interrupts.
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* @t7xx_dev: MTK device.
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* @enable: Enable/disable.
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*
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* Enable or disable device interrupts.
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*/
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static void t7xx_pcie_mac_enable_disable_int(struct t7xx_pci_dev *t7xx_dev, bool enable)
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{
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u32 value;
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value = ioread32(IREG_BASE(t7xx_dev) + ISTAT_HST_CTRL);
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if (enable)
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value &= ~ISTAT_HST_CTRL_DIS;
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else
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value |= ISTAT_HST_CTRL_DIS;
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iowrite32(value, IREG_BASE(t7xx_dev) + ISTAT_HST_CTRL);
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}
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void t7xx_pcie_mac_interrupts_en(struct t7xx_pci_dev *t7xx_dev)
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{
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t7xx_pcie_mac_enable_disable_int(t7xx_dev, true);
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}
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void t7xx_pcie_mac_interrupts_dis(struct t7xx_pci_dev *t7xx_dev)
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{
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t7xx_pcie_mac_enable_disable_int(t7xx_dev, false);
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}
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/**
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* t7xx_pcie_mac_clear_set_int() - Clear/set interrupt by type.
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* @t7xx_dev: MTK device.
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* @int_type: Interrupt type.
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* @clear: Clear/set.
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*
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* Clear or set device interrupt by type.
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*/
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static void t7xx_pcie_mac_clear_set_int(struct t7xx_pci_dev *t7xx_dev,
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enum t7xx_int int_type, bool clear)
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{
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void __iomem *reg;
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u32 val;
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if (clear)
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reg = IREG_BASE(t7xx_dev) + IMASK_HOST_MSIX_CLR_GRP0_0;
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else
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reg = IREG_BASE(t7xx_dev) + IMASK_HOST_MSIX_SET_GRP0_0;
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val = BIT(EXT_INT_START + int_type);
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iowrite32(val, reg);
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}
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void t7xx_pcie_mac_clear_int(struct t7xx_pci_dev *t7xx_dev, enum t7xx_int int_type)
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{
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t7xx_pcie_mac_clear_set_int(t7xx_dev, int_type, true);
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}
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void t7xx_pcie_mac_set_int(struct t7xx_pci_dev *t7xx_dev, enum t7xx_int int_type)
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{
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t7xx_pcie_mac_clear_set_int(t7xx_dev, int_type, false);
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}
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/**
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* t7xx_pcie_mac_clear_int_status() - Clear interrupt status by type.
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* @t7xx_dev: MTK device.
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* @int_type: Interrupt type.
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*
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* Enable or disable device interrupts' status by type.
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*/
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void t7xx_pcie_mac_clear_int_status(struct t7xx_pci_dev *t7xx_dev, enum t7xx_int int_type)
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{
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void __iomem *reg = IREG_BASE(t7xx_dev) + MSIX_ISTAT_HST_GRP0_0;
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u32 val = BIT(EXT_INT_START + int_type);
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iowrite32(val, reg);
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}
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/**
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* t7xx_pcie_set_mac_msix_cfg() - Write MSIX control configuration.
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* @t7xx_dev: MTK device.
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* @irq_count: Number of MSIX IRQ vectors.
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*
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* Write IRQ count to device.
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*/
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void t7xx_pcie_set_mac_msix_cfg(struct t7xx_pci_dev *t7xx_dev, unsigned int irq_count)
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{
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u32 val = ffs(irq_count) * 2 - 1;
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iowrite32(val, IREG_BASE(t7xx_dev) + T7XX_PCIE_CFG_MSIX);
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}
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