632 lines
15 KiB
C
632 lines
15 KiB
C
// SPDX-License-Identifier: GPL-2.0-only
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/*
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* (c) Copyright 2002-2010, Ralink Technology, Inc.
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* Copyright (C) 2014 Felix Fietkau <nbd@openwrt.org>
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* Copyright (C) 2015 Jakub Kicinski <kubakici@wp.pl>
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*/
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#include "mt7601u.h"
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#include "eeprom.h"
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#include "trace.h"
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#include "mcu.h"
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#include "initvals.h"
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static void
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mt7601u_set_wlan_state(struct mt7601u_dev *dev, u32 val, bool enable)
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{
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int i;
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/* Note: we don't turn off WLAN_CLK because that makes the device
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* not respond properly on the probe path.
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* In case anyone (PSM?) wants to use this function we can
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* bring the clock stuff back and fixup the probe path.
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*/
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if (enable)
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val |= (MT_WLAN_FUN_CTRL_WLAN_EN |
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MT_WLAN_FUN_CTRL_WLAN_CLK_EN);
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else
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val &= ~(MT_WLAN_FUN_CTRL_WLAN_EN);
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mt7601u_wr(dev, MT_WLAN_FUN_CTRL, val);
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udelay(20);
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if (enable) {
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set_bit(MT7601U_STATE_WLAN_RUNNING, &dev->state);
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} else {
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clear_bit(MT7601U_STATE_WLAN_RUNNING, &dev->state);
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return;
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}
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for (i = 200; i; i--) {
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val = mt7601u_rr(dev, MT_CMB_CTRL);
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if (val & MT_CMB_CTRL_XTAL_RDY && val & MT_CMB_CTRL_PLL_LD)
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break;
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udelay(20);
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}
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/* Note: vendor driver tries to disable/enable wlan here and retry
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* but the code which does it is so buggy it must have never
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* triggered, so don't bother.
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*/
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if (!i)
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dev_err(dev->dev, "Error: PLL and XTAL check failed!\n");
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}
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static void mt7601u_chip_onoff(struct mt7601u_dev *dev, bool enable, bool reset)
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{
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u32 val;
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mutex_lock(&dev->hw_atomic_mutex);
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val = mt7601u_rr(dev, MT_WLAN_FUN_CTRL);
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if (reset) {
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val |= MT_WLAN_FUN_CTRL_GPIO_OUT_EN;
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val &= ~MT_WLAN_FUN_CTRL_FRC_WL_ANT_SEL;
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if (val & MT_WLAN_FUN_CTRL_WLAN_EN) {
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val |= (MT_WLAN_FUN_CTRL_WLAN_RESET |
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MT_WLAN_FUN_CTRL_WLAN_RESET_RF);
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mt7601u_wr(dev, MT_WLAN_FUN_CTRL, val);
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udelay(20);
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val &= ~(MT_WLAN_FUN_CTRL_WLAN_RESET |
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MT_WLAN_FUN_CTRL_WLAN_RESET_RF);
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}
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}
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mt7601u_wr(dev, MT_WLAN_FUN_CTRL, val);
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udelay(20);
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mt7601u_set_wlan_state(dev, val, enable);
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mutex_unlock(&dev->hw_atomic_mutex);
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}
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static void mt7601u_reset_csr_bbp(struct mt7601u_dev *dev)
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{
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mt7601u_wr(dev, MT_MAC_SYS_CTRL, (MT_MAC_SYS_CTRL_RESET_CSR |
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MT_MAC_SYS_CTRL_RESET_BBP));
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mt7601u_wr(dev, MT_USB_DMA_CFG, 0);
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msleep(1);
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mt7601u_wr(dev, MT_MAC_SYS_CTRL, 0);
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}
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static void mt7601u_init_usb_dma(struct mt7601u_dev *dev)
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{
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u32 val;
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val = FIELD_PREP(MT_USB_DMA_CFG_RX_BULK_AGG_TOUT, MT_USB_AGGR_TIMEOUT) |
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FIELD_PREP(MT_USB_DMA_CFG_RX_BULK_AGG_LMT,
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MT_USB_AGGR_SIZE_LIMIT) |
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MT_USB_DMA_CFG_RX_BULK_EN |
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MT_USB_DMA_CFG_TX_BULK_EN;
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if (dev->in_max_packet == 512)
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val |= MT_USB_DMA_CFG_RX_BULK_AGG_EN;
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mt7601u_wr(dev, MT_USB_DMA_CFG, val);
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val |= MT_USB_DMA_CFG_UDMA_RX_WL_DROP;
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mt7601u_wr(dev, MT_USB_DMA_CFG, val);
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val &= ~MT_USB_DMA_CFG_UDMA_RX_WL_DROP;
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mt7601u_wr(dev, MT_USB_DMA_CFG, val);
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}
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static int mt7601u_init_bbp(struct mt7601u_dev *dev)
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{
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int ret;
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ret = mt7601u_wait_bbp_ready(dev);
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if (ret)
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return ret;
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ret = mt7601u_write_reg_pairs(dev, MT_MCU_MEMMAP_BBP, bbp_common_vals,
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ARRAY_SIZE(bbp_common_vals));
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if (ret)
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return ret;
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return mt7601u_write_reg_pairs(dev, MT_MCU_MEMMAP_BBP, bbp_chip_vals,
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ARRAY_SIZE(bbp_chip_vals));
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}
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static void
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mt76_init_beacon_offsets(struct mt7601u_dev *dev)
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{
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u16 base = MT_BEACON_BASE;
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u32 regs[4] = {};
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int i;
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for (i = 0; i < 16; i++) {
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u16 addr = dev->beacon_offsets[i];
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regs[i / 4] |= ((addr - base) / 64) << (8 * (i % 4));
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}
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for (i = 0; i < 4; i++)
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mt7601u_wr(dev, MT_BCN_OFFSET(i), regs[i]);
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}
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static int mt7601u_write_mac_initvals(struct mt7601u_dev *dev)
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{
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int ret;
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ret = mt7601u_write_reg_pairs(dev, MT_MCU_MEMMAP_WLAN, mac_common_vals,
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ARRAY_SIZE(mac_common_vals));
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if (ret)
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return ret;
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ret = mt7601u_write_reg_pairs(dev, MT_MCU_MEMMAP_WLAN,
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mac_chip_vals, ARRAY_SIZE(mac_chip_vals));
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if (ret)
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return ret;
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mt76_init_beacon_offsets(dev);
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mt7601u_wr(dev, MT_AUX_CLK_CFG, 0);
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return 0;
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}
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static int mt7601u_init_wcid_mem(struct mt7601u_dev *dev)
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{
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u32 *vals;
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int i, ret;
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vals = kmalloc(sizeof(*vals) * N_WCIDS * 2, GFP_KERNEL);
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if (!vals)
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return -ENOMEM;
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for (i = 0; i < N_WCIDS; i++) {
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vals[i * 2] = 0xffffffff;
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vals[i * 2 + 1] = 0x00ffffff;
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}
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ret = mt7601u_burst_write_regs(dev, MT_WCID_ADDR_BASE,
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vals, N_WCIDS * 2);
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kfree(vals);
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return ret;
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}
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static int mt7601u_init_key_mem(struct mt7601u_dev *dev)
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{
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u32 vals[4] = {};
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return mt7601u_burst_write_regs(dev, MT_SKEY_MODE_BASE_0,
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vals, ARRAY_SIZE(vals));
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}
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static int mt7601u_init_wcid_attr_mem(struct mt7601u_dev *dev)
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{
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u32 *vals;
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int i, ret;
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vals = kmalloc(sizeof(*vals) * N_WCIDS * 2, GFP_KERNEL);
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if (!vals)
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return -ENOMEM;
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for (i = 0; i < N_WCIDS * 2; i++)
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vals[i] = 1;
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ret = mt7601u_burst_write_regs(dev, MT_WCID_ATTR_BASE,
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vals, N_WCIDS * 2);
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kfree(vals);
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return ret;
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}
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static void mt7601u_reset_counters(struct mt7601u_dev *dev)
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{
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mt7601u_rr(dev, MT_RX_STA_CNT0);
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mt7601u_rr(dev, MT_RX_STA_CNT1);
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mt7601u_rr(dev, MT_RX_STA_CNT2);
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mt7601u_rr(dev, MT_TX_STA_CNT0);
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mt7601u_rr(dev, MT_TX_STA_CNT1);
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mt7601u_rr(dev, MT_TX_STA_CNT2);
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}
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int mt7601u_mac_start(struct mt7601u_dev *dev)
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{
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mt7601u_wr(dev, MT_MAC_SYS_CTRL, MT_MAC_SYS_CTRL_ENABLE_TX);
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if (!mt76_poll(dev, MT_WPDMA_GLO_CFG, MT_WPDMA_GLO_CFG_TX_DMA_BUSY |
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MT_WPDMA_GLO_CFG_RX_DMA_BUSY, 0, 200000))
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return -ETIMEDOUT;
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dev->rxfilter = MT_RX_FILTR_CFG_CRC_ERR |
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MT_RX_FILTR_CFG_PHY_ERR | MT_RX_FILTR_CFG_PROMISC |
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MT_RX_FILTR_CFG_VER_ERR | MT_RX_FILTR_CFG_DUP |
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MT_RX_FILTR_CFG_CFACK | MT_RX_FILTR_CFG_CFEND |
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MT_RX_FILTR_CFG_ACK | MT_RX_FILTR_CFG_CTS |
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MT_RX_FILTR_CFG_RTS | MT_RX_FILTR_CFG_PSPOLL |
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MT_RX_FILTR_CFG_BA | MT_RX_FILTR_CFG_CTRL_RSV;
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mt7601u_wr(dev, MT_RX_FILTR_CFG, dev->rxfilter);
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mt7601u_wr(dev, MT_MAC_SYS_CTRL,
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MT_MAC_SYS_CTRL_ENABLE_TX | MT_MAC_SYS_CTRL_ENABLE_RX);
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if (!mt76_poll(dev, MT_WPDMA_GLO_CFG, MT_WPDMA_GLO_CFG_TX_DMA_BUSY |
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MT_WPDMA_GLO_CFG_RX_DMA_BUSY, 0, 50))
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return -ETIMEDOUT;
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return 0;
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}
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static void mt7601u_mac_stop_hw(struct mt7601u_dev *dev)
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{
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int i, ok;
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if (test_bit(MT7601U_STATE_REMOVED, &dev->state))
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return;
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mt76_clear(dev, MT_BEACON_TIME_CFG, MT_BEACON_TIME_CFG_TIMER_EN |
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MT_BEACON_TIME_CFG_SYNC_MODE | MT_BEACON_TIME_CFG_TBTT_EN |
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MT_BEACON_TIME_CFG_BEACON_TX);
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if (!mt76_poll(dev, MT_USB_DMA_CFG, MT_USB_DMA_CFG_TX_BUSY, 0, 1000))
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dev_warn(dev->dev, "Warning: TX DMA did not stop!\n");
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/* Page count on TxQ */
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i = 200;
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while (i-- && ((mt76_rr(dev, 0x0438) & 0xffffffff) ||
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(mt76_rr(dev, 0x0a30) & 0x000000ff) ||
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(mt76_rr(dev, 0x0a34) & 0x00ff00ff)))
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msleep(10);
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if (!mt76_poll(dev, MT_MAC_STATUS, MT_MAC_STATUS_TX, 0, 1000))
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dev_warn(dev->dev, "Warning: MAC TX did not stop!\n");
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mt76_clear(dev, MT_MAC_SYS_CTRL, MT_MAC_SYS_CTRL_ENABLE_RX |
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MT_MAC_SYS_CTRL_ENABLE_TX);
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/* Page count on RxQ */
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ok = 0;
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i = 200;
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while (i--) {
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if (!(mt76_rr(dev, MT_RXQ_STA) & 0x00ff0000) &&
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!mt76_rr(dev, 0x0a30) &&
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!mt76_rr(dev, 0x0a34)) {
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if (ok++ > 5)
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break;
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continue;
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}
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msleep(1);
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}
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if (!mt76_poll(dev, MT_MAC_STATUS, MT_MAC_STATUS_RX, 0, 1000))
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dev_warn(dev->dev, "Warning: MAC RX did not stop!\n");
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if (!mt76_poll(dev, MT_USB_DMA_CFG, MT_USB_DMA_CFG_RX_BUSY, 0, 1000))
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dev_warn(dev->dev, "Warning: RX DMA did not stop!\n");
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}
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void mt7601u_mac_stop(struct mt7601u_dev *dev)
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{
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mt7601u_mac_stop_hw(dev);
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flush_delayed_work(&dev->stat_work);
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cancel_delayed_work_sync(&dev->stat_work);
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}
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static void mt7601u_stop_hardware(struct mt7601u_dev *dev)
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{
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mt7601u_chip_onoff(dev, false, false);
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}
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int mt7601u_init_hardware(struct mt7601u_dev *dev)
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{
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static const u16 beacon_offsets[16] = {
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/* 512 byte per beacon */
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0xc000, 0xc200, 0xc400, 0xc600,
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0xc800, 0xca00, 0xcc00, 0xce00,
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0xd000, 0xd200, 0xd400, 0xd600,
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0xd800, 0xda00, 0xdc00, 0xde00
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};
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int ret;
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dev->beacon_offsets = beacon_offsets;
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mt7601u_chip_onoff(dev, true, false);
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ret = mt7601u_wait_asic_ready(dev);
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if (ret)
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goto err;
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ret = mt7601u_mcu_init(dev);
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if (ret)
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goto err;
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if (!mt76_poll_msec(dev, MT_WPDMA_GLO_CFG,
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MT_WPDMA_GLO_CFG_TX_DMA_BUSY |
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MT_WPDMA_GLO_CFG_RX_DMA_BUSY, 0, 100)) {
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ret = -EIO;
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goto err;
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}
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/* Wait for ASIC ready after FW load. */
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ret = mt7601u_wait_asic_ready(dev);
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if (ret)
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goto err;
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mt7601u_reset_csr_bbp(dev);
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mt7601u_init_usb_dma(dev);
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ret = mt7601u_mcu_cmd_init(dev);
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if (ret)
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goto err;
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ret = mt7601u_dma_init(dev);
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if (ret)
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goto err_mcu;
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ret = mt7601u_write_mac_initvals(dev);
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if (ret)
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goto err_rx;
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if (!mt76_poll_msec(dev, MT_MAC_STATUS,
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MT_MAC_STATUS_TX | MT_MAC_STATUS_RX, 0, 100)) {
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ret = -EIO;
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goto err_rx;
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}
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ret = mt7601u_init_bbp(dev);
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if (ret)
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goto err_rx;
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ret = mt7601u_init_wcid_mem(dev);
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if (ret)
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goto err_rx;
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ret = mt7601u_init_key_mem(dev);
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if (ret)
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goto err_rx;
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ret = mt7601u_init_wcid_attr_mem(dev);
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if (ret)
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goto err_rx;
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mt76_clear(dev, MT_BEACON_TIME_CFG, (MT_BEACON_TIME_CFG_TIMER_EN |
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MT_BEACON_TIME_CFG_SYNC_MODE |
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MT_BEACON_TIME_CFG_TBTT_EN |
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MT_BEACON_TIME_CFG_BEACON_TX));
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mt7601u_reset_counters(dev);
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mt7601u_rmw(dev, MT_US_CYC_CFG, MT_US_CYC_CNT, 0x1e);
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mt7601u_wr(dev, MT_TXOP_CTRL_CFG,
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FIELD_PREP(MT_TXOP_TRUN_EN, 0x3f) |
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FIELD_PREP(MT_TXOP_EXT_CCA_DLY, 0x58));
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ret = mt7601u_eeprom_init(dev);
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if (ret)
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goto err_rx;
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ret = mt7601u_phy_init(dev);
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if (ret)
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goto err_rx;
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mt7601u_set_rx_path(dev, 0);
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mt7601u_set_tx_dac(dev, 0);
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mt7601u_mac_set_ctrlch(dev, false);
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mt7601u_bbp_set_ctrlch(dev, false);
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mt7601u_bbp_set_bw(dev, MT_BW_20);
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return 0;
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err_rx:
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mt7601u_dma_cleanup(dev);
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err_mcu:
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mt7601u_mcu_cmd_deinit(dev);
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err:
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mt7601u_chip_onoff(dev, false, false);
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return ret;
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}
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void mt7601u_cleanup(struct mt7601u_dev *dev)
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{
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if (!test_and_clear_bit(MT7601U_STATE_INITIALIZED, &dev->state))
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return;
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mt7601u_stop_hardware(dev);
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mt7601u_dma_cleanup(dev);
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mt7601u_mcu_cmd_deinit(dev);
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}
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struct mt7601u_dev *mt7601u_alloc_device(struct device *pdev)
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{
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struct ieee80211_hw *hw;
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struct mt7601u_dev *dev;
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hw = ieee80211_alloc_hw(sizeof(*dev), &mt7601u_ops);
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if (!hw)
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return NULL;
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dev = hw->priv;
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dev->dev = pdev;
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dev->hw = hw;
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mutex_init(&dev->vendor_req_mutex);
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mutex_init(&dev->reg_atomic_mutex);
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mutex_init(&dev->hw_atomic_mutex);
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mutex_init(&dev->mutex);
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spin_lock_init(&dev->tx_lock);
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spin_lock_init(&dev->rx_lock);
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spin_lock_init(&dev->lock);
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spin_lock_init(&dev->mac_lock);
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spin_lock_init(&dev->con_mon_lock);
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atomic_set(&dev->avg_ampdu_len, 1);
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skb_queue_head_init(&dev->tx_skb_done);
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dev->stat_wq = alloc_workqueue("mt7601u", WQ_UNBOUND, 0);
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if (!dev->stat_wq) {
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ieee80211_free_hw(hw);
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return NULL;
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}
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return dev;
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}
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#define CHAN2G(_idx, _freq) { \
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.band = NL80211_BAND_2GHZ, \
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.center_freq = (_freq), \
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.hw_value = (_idx), \
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.max_power = 30, \
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}
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static const struct ieee80211_channel mt76_channels_2ghz[] = {
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CHAN2G(1, 2412),
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CHAN2G(2, 2417),
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CHAN2G(3, 2422),
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CHAN2G(4, 2427),
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CHAN2G(5, 2432),
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CHAN2G(6, 2437),
|
|
CHAN2G(7, 2442),
|
|
CHAN2G(8, 2447),
|
|
CHAN2G(9, 2452),
|
|
CHAN2G(10, 2457),
|
|
CHAN2G(11, 2462),
|
|
CHAN2G(12, 2467),
|
|
CHAN2G(13, 2472),
|
|
CHAN2G(14, 2484),
|
|
};
|
|
|
|
#define CCK_RATE(_idx, _rate) { \
|
|
.bitrate = _rate, \
|
|
.flags = IEEE80211_RATE_SHORT_PREAMBLE, \
|
|
.hw_value = (MT_PHY_TYPE_CCK << 8) | _idx, \
|
|
.hw_value_short = (MT_PHY_TYPE_CCK << 8) | (8 + _idx), \
|
|
}
|
|
|
|
#define OFDM_RATE(_idx, _rate) { \
|
|
.bitrate = _rate, \
|
|
.hw_value = (MT_PHY_TYPE_OFDM << 8) | _idx, \
|
|
.hw_value_short = (MT_PHY_TYPE_OFDM << 8) | _idx, \
|
|
}
|
|
|
|
static struct ieee80211_rate mt76_rates[] = {
|
|
CCK_RATE(0, 10),
|
|
CCK_RATE(1, 20),
|
|
CCK_RATE(2, 55),
|
|
CCK_RATE(3, 110),
|
|
OFDM_RATE(0, 60),
|
|
OFDM_RATE(1, 90),
|
|
OFDM_RATE(2, 120),
|
|
OFDM_RATE(3, 180),
|
|
OFDM_RATE(4, 240),
|
|
OFDM_RATE(5, 360),
|
|
OFDM_RATE(6, 480),
|
|
OFDM_RATE(7, 540),
|
|
};
|
|
|
|
static int
|
|
mt76_init_sband(struct mt7601u_dev *dev, struct ieee80211_supported_band *sband,
|
|
const struct ieee80211_channel *chan, int n_chan,
|
|
struct ieee80211_rate *rates, int n_rates)
|
|
{
|
|
struct ieee80211_sta_ht_cap *ht_cap;
|
|
void *chanlist;
|
|
int size;
|
|
|
|
size = n_chan * sizeof(*chan);
|
|
chanlist = devm_kmemdup(dev->dev, chan, size, GFP_KERNEL);
|
|
if (!chanlist)
|
|
return -ENOMEM;
|
|
|
|
sband->channels = chanlist;
|
|
sband->n_channels = n_chan;
|
|
sband->bitrates = rates;
|
|
sband->n_bitrates = n_rates;
|
|
|
|
ht_cap = &sband->ht_cap;
|
|
ht_cap->ht_supported = true;
|
|
ht_cap->cap = IEEE80211_HT_CAP_SUP_WIDTH_20_40 |
|
|
IEEE80211_HT_CAP_GRN_FLD |
|
|
IEEE80211_HT_CAP_SGI_20 |
|
|
IEEE80211_HT_CAP_SGI_40 |
|
|
(1 << IEEE80211_HT_CAP_RX_STBC_SHIFT);
|
|
|
|
ht_cap->mcs.rx_mask[0] = 0xff;
|
|
ht_cap->mcs.rx_mask[4] = 0x1;
|
|
ht_cap->mcs.tx_params = IEEE80211_HT_MCS_TX_DEFINED;
|
|
ht_cap->ampdu_factor = IEEE80211_HT_MAX_AMPDU_64K;
|
|
ht_cap->ampdu_density = IEEE80211_HT_MPDU_DENSITY_2;
|
|
|
|
dev->chandef.chan = &sband->channels[0];
|
|
|
|
return 0;
|
|
}
|
|
|
|
static int
|
|
mt76_init_sband_2g(struct mt7601u_dev *dev)
|
|
{
|
|
dev->sband_2g = devm_kzalloc(dev->dev, sizeof(*dev->sband_2g),
|
|
GFP_KERNEL);
|
|
if (!dev->sband_2g)
|
|
return -ENOMEM;
|
|
|
|
dev->hw->wiphy->bands[NL80211_BAND_2GHZ] = dev->sband_2g;
|
|
|
|
WARN_ON(dev->ee->reg.start - 1 + dev->ee->reg.num >
|
|
ARRAY_SIZE(mt76_channels_2ghz));
|
|
|
|
return mt76_init_sband(dev, dev->sband_2g,
|
|
&mt76_channels_2ghz[dev->ee->reg.start - 1],
|
|
dev->ee->reg.num,
|
|
mt76_rates, ARRAY_SIZE(mt76_rates));
|
|
}
|
|
|
|
int mt7601u_register_device(struct mt7601u_dev *dev)
|
|
{
|
|
struct ieee80211_hw *hw = dev->hw;
|
|
struct wiphy *wiphy = hw->wiphy;
|
|
int ret;
|
|
|
|
/* Reserve WCID 0 for mcast - thanks to this APs WCID will go to
|
|
* entry no. 1 like it does in the vendor driver.
|
|
*/
|
|
dev->wcid_mask[0] |= 1;
|
|
|
|
/* init fake wcid for monitor interfaces */
|
|
dev->mon_wcid = devm_kmalloc(dev->dev, sizeof(*dev->mon_wcid),
|
|
GFP_KERNEL);
|
|
if (!dev->mon_wcid)
|
|
return -ENOMEM;
|
|
dev->mon_wcid->idx = 0xff;
|
|
dev->mon_wcid->hw_key_idx = -1;
|
|
|
|
SET_IEEE80211_DEV(hw, dev->dev);
|
|
|
|
hw->queues = 4;
|
|
ieee80211_hw_set(hw, SIGNAL_DBM);
|
|
ieee80211_hw_set(hw, PS_NULLFUNC_STACK);
|
|
ieee80211_hw_set(hw, SUPPORTS_HT_CCK_RATES);
|
|
ieee80211_hw_set(hw, AMPDU_AGGREGATION);
|
|
ieee80211_hw_set(hw, SUPPORTS_RC_TABLE);
|
|
ieee80211_hw_set(hw, MFP_CAPABLE);
|
|
hw->max_rates = 1;
|
|
hw->max_report_rates = 7;
|
|
hw->max_rate_tries = 1;
|
|
|
|
hw->sta_data_size = sizeof(struct mt76_sta);
|
|
hw->vif_data_size = sizeof(struct mt76_vif);
|
|
|
|
SET_IEEE80211_PERM_ADDR(hw, dev->macaddr);
|
|
|
|
wiphy->features |= NL80211_FEATURE_ACTIVE_MONITOR;
|
|
wiphy->interface_modes = BIT(NL80211_IFTYPE_STATION);
|
|
wiphy->flags |= WIPHY_FLAG_SUPPORTS_TDLS;
|
|
|
|
wiphy_ext_feature_set(wiphy, NL80211_EXT_FEATURE_CQM_RSSI_LIST);
|
|
|
|
ret = mt76_init_sband_2g(dev);
|
|
if (ret)
|
|
return ret;
|
|
|
|
INIT_DELAYED_WORK(&dev->mac_work, mt7601u_mac_work);
|
|
INIT_DELAYED_WORK(&dev->stat_work, mt7601u_tx_stat);
|
|
|
|
ret = ieee80211_register_hw(hw);
|
|
if (ret)
|
|
return ret;
|
|
|
|
mt7601u_init_debugfs(dev);
|
|
|
|
return 0;
|
|
}
|