160 lines
4.0 KiB
C
160 lines
4.0 KiB
C
// SPDX-License-Identifier: GPL-2.0
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// Copyright (c) 2018-2019 MediaTek Inc.
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/* A library for MediaTek SGMII circuit
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*
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* Author: Sean Wang <sean.wang@mediatek.com>
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*
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*/
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#include <linux/mfd/syscon.h>
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#include <linux/of.h>
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#include <linux/phylink.h>
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#include <linux/regmap.h>
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#include "mtk_eth_soc.h"
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static struct mtk_pcs *pcs_to_mtk_pcs(struct phylink_pcs *pcs)
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{
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return container_of(pcs, struct mtk_pcs, pcs);
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}
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/* For SGMII interface mode */
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static int mtk_pcs_setup_mode_an(struct mtk_pcs *mpcs)
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{
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unsigned int val;
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/* Setup the link timer and QPHY power up inside SGMIISYS */
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regmap_write(mpcs->regmap, SGMSYS_PCS_LINK_TIMER,
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SGMII_LINK_TIMER_DEFAULT);
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regmap_read(mpcs->regmap, SGMSYS_SGMII_MODE, &val);
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val |= SGMII_REMOTE_FAULT_DIS;
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regmap_write(mpcs->regmap, SGMSYS_SGMII_MODE, val);
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regmap_read(mpcs->regmap, SGMSYS_PCS_CONTROL_1, &val);
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val |= SGMII_AN_RESTART;
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regmap_write(mpcs->regmap, SGMSYS_PCS_CONTROL_1, val);
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regmap_read(mpcs->regmap, SGMSYS_QPHY_PWR_STATE_CTRL, &val);
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val &= ~SGMII_PHYA_PWD;
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regmap_write(mpcs->regmap, SGMSYS_QPHY_PWR_STATE_CTRL, val);
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return 0;
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}
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/* For 1000BASE-X and 2500BASE-X interface modes, which operate at a
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* fixed speed.
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*/
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static int mtk_pcs_setup_mode_force(struct mtk_pcs *mpcs,
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phy_interface_t interface)
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{
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unsigned int val;
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regmap_read(mpcs->regmap, mpcs->ana_rgc3, &val);
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val &= ~RG_PHY_SPEED_MASK;
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if (interface == PHY_INTERFACE_MODE_2500BASEX)
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val |= RG_PHY_SPEED_3_125G;
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regmap_write(mpcs->regmap, mpcs->ana_rgc3, val);
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/* Disable SGMII AN */
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regmap_read(mpcs->regmap, SGMSYS_PCS_CONTROL_1, &val);
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val &= ~SGMII_AN_ENABLE;
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regmap_write(mpcs->regmap, SGMSYS_PCS_CONTROL_1, val);
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/* Set the speed etc but leave the duplex unchanged */
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regmap_read(mpcs->regmap, SGMSYS_SGMII_MODE, &val);
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val &= SGMII_DUPLEX_FULL | ~SGMII_IF_MODE_MASK;
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val |= SGMII_SPEED_1000;
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regmap_write(mpcs->regmap, SGMSYS_SGMII_MODE, val);
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/* Release PHYA power down state */
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regmap_read(mpcs->regmap, SGMSYS_QPHY_PWR_STATE_CTRL, &val);
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val &= ~SGMII_PHYA_PWD;
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regmap_write(mpcs->regmap, SGMSYS_QPHY_PWR_STATE_CTRL, val);
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return 0;
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}
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static int mtk_pcs_config(struct phylink_pcs *pcs, unsigned int mode,
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phy_interface_t interface,
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const unsigned long *advertising,
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bool permit_pause_to_mac)
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{
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struct mtk_pcs *mpcs = pcs_to_mtk_pcs(pcs);
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int err = 0;
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/* Setup SGMIISYS with the determined property */
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if (interface != PHY_INTERFACE_MODE_SGMII)
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err = mtk_pcs_setup_mode_force(mpcs, interface);
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else if (phylink_autoneg_inband(mode))
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err = mtk_pcs_setup_mode_an(mpcs);
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return err;
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}
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static void mtk_pcs_restart_an(struct phylink_pcs *pcs)
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{
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struct mtk_pcs *mpcs = pcs_to_mtk_pcs(pcs);
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unsigned int val;
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regmap_read(mpcs->regmap, SGMSYS_PCS_CONTROL_1, &val);
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val |= SGMII_AN_RESTART;
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regmap_write(mpcs->regmap, SGMSYS_PCS_CONTROL_1, val);
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}
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static void mtk_pcs_link_up(struct phylink_pcs *pcs, unsigned int mode,
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phy_interface_t interface, int speed, int duplex)
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{
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struct mtk_pcs *mpcs = pcs_to_mtk_pcs(pcs);
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unsigned int val;
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if (!phy_interface_mode_is_8023z(interface))
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return;
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/* SGMII force duplex setting */
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regmap_read(mpcs->regmap, SGMSYS_SGMII_MODE, &val);
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val &= ~SGMII_DUPLEX_FULL;
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if (duplex == DUPLEX_FULL)
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val |= SGMII_DUPLEX_FULL;
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regmap_write(mpcs->regmap, SGMSYS_SGMII_MODE, val);
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}
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static const struct phylink_pcs_ops mtk_pcs_ops = {
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.pcs_config = mtk_pcs_config,
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.pcs_an_restart = mtk_pcs_restart_an,
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.pcs_link_up = mtk_pcs_link_up,
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};
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int mtk_sgmii_init(struct mtk_sgmii *ss, struct device_node *r, u32 ana_rgc3)
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{
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struct device_node *np;
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int i;
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for (i = 0; i < MTK_MAX_DEVS; i++) {
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np = of_parse_phandle(r, "mediatek,sgmiisys", i);
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if (!np)
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break;
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ss->pcs[i].ana_rgc3 = ana_rgc3;
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ss->pcs[i].regmap = syscon_node_to_regmap(np);
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of_node_put(np);
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if (IS_ERR(ss->pcs[i].regmap))
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return PTR_ERR(ss->pcs[i].regmap);
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ss->pcs[i].pcs.ops = &mtk_pcs_ops;
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}
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return 0;
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}
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struct phylink_pcs *mtk_sgmii_select_pcs(struct mtk_sgmii *ss, int id)
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{
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if (!ss->pcs[id].regmap)
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return NULL;
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return &ss->pcs[id].pcs;
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}
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