911 lines
27 KiB
C
911 lines
27 KiB
C
/* SPDX-License-Identifier: GPL-2.0 */
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/* Marvell RVU Admin Function driver
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*
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* Copyright (C) 2018 Marvell.
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*
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*/
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#ifndef RVU_H
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#define RVU_H
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#include <linux/pci.h>
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#include <net/devlink.h>
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#include "rvu_struct.h"
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#include "rvu_devlink.h"
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#include "common.h"
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#include "mbox.h"
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#include "npc.h"
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#include "rvu_reg.h"
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/* PCI device IDs */
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#define PCI_DEVID_OCTEONTX2_RVU_AF 0xA065
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#define PCI_DEVID_OCTEONTX2_LBK 0xA061
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/* Subsystem Device ID */
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#define PCI_SUBSYS_DEVID_98XX 0xB100
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#define PCI_SUBSYS_DEVID_96XX 0xB200
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#define PCI_SUBSYS_DEVID_CN10K_A 0xB900
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#define PCI_SUBSYS_DEVID_CNF10K_B 0xBC00
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#define PCI_SUBSYS_DEVID_CN10K_B 0xBD00
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/* PCI BAR nos */
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#define PCI_AF_REG_BAR_NUM 0
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#define PCI_PF_REG_BAR_NUM 2
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#define PCI_MBOX_BAR_NUM 4
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#define NAME_SIZE 32
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#define MAX_NIX_BLKS 2
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#define MAX_CPT_BLKS 2
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/* PF_FUNC */
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#define RVU_PFVF_PF_SHIFT 10
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#define RVU_PFVF_PF_MASK 0x3F
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#define RVU_PFVF_FUNC_SHIFT 0
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#define RVU_PFVF_FUNC_MASK 0x3FF
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#ifdef CONFIG_DEBUG_FS
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struct dump_ctx {
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int lf;
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int id;
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bool all;
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};
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struct cpt_ctx {
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int blkaddr;
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struct rvu *rvu;
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};
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struct rvu_debugfs {
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struct dentry *root;
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struct dentry *cgx_root;
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struct dentry *cgx;
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struct dentry *lmac;
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struct dentry *npa;
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struct dentry *nix;
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struct dentry *npc;
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struct dentry *cpt;
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struct dentry *mcs_root;
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struct dentry *mcs;
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struct dentry *mcs_rx;
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struct dentry *mcs_tx;
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struct dump_ctx npa_aura_ctx;
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struct dump_ctx npa_pool_ctx;
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struct dump_ctx nix_cq_ctx;
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struct dump_ctx nix_rq_ctx;
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struct dump_ctx nix_sq_ctx;
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struct cpt_ctx cpt_ctx[MAX_CPT_BLKS];
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int npa_qsize_id;
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int nix_qsize_id;
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};
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#endif
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struct rvu_work {
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struct work_struct work;
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struct rvu *rvu;
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int num_msgs;
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int up_num_msgs;
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};
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struct rsrc_bmap {
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unsigned long *bmap; /* Pointer to resource bitmap */
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u16 max; /* Max resource id or count */
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};
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struct rvu_block {
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struct rsrc_bmap lf;
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struct admin_queue *aq; /* NIX/NPA AQ */
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u16 *fn_map; /* LF to pcifunc mapping */
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bool multislot;
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bool implemented;
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u8 addr; /* RVU_BLOCK_ADDR_E */
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u8 type; /* RVU_BLOCK_TYPE_E */
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u8 lfshift;
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u64 lookup_reg;
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u64 pf_lfcnt_reg;
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u64 vf_lfcnt_reg;
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u64 lfcfg_reg;
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u64 msixcfg_reg;
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u64 lfreset_reg;
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unsigned char name[NAME_SIZE];
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struct rvu *rvu;
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};
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struct nix_mcast {
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struct qmem *mce_ctx;
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struct qmem *mcast_buf;
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int replay_pkind;
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int next_free_mce;
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struct mutex mce_lock; /* Serialize MCE updates */
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};
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struct nix_mce_list {
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struct hlist_head head;
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int count;
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int max;
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};
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/* layer metadata to uniquely identify a packet header field */
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struct npc_layer_mdata {
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u8 lid;
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u8 ltype;
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u8 hdr;
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u8 key;
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u8 len;
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};
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/* Structure to represent a field present in the
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* generated key. A key field may present anywhere and can
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* be of any size in the generated key. Once this structure
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* is populated for fields of interest then field's presence
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* and location (if present) can be known.
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*/
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struct npc_key_field {
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/* Masks where all set bits indicate position
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* of a field in the key
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*/
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u64 kw_mask[NPC_MAX_KWS_IN_KEY];
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/* Number of words in the key a field spans. If a field is
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* of 16 bytes and key offset is 4 then the field will use
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* 4 bytes in KW0, 8 bytes in KW1 and 4 bytes in KW2 and
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* nr_kws will be 3(KW0, KW1 and KW2).
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*/
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int nr_kws;
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/* used by packet header fields */
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struct npc_layer_mdata layer_mdata;
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};
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struct npc_mcam {
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struct rsrc_bmap counters;
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struct mutex lock; /* MCAM entries and counters update lock */
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unsigned long *bmap; /* bitmap, 0 => bmap_entries */
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unsigned long *bmap_reverse; /* Reverse bitmap, bmap_entries => 0 */
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u16 bmap_entries; /* Number of unreserved MCAM entries */
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u16 bmap_fcnt; /* MCAM entries free count */
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u16 *entry2pfvf_map;
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u16 *entry2cntr_map;
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u16 *cntr2pfvf_map;
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u16 *cntr_refcnt;
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u16 *entry2target_pffunc;
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u8 keysize; /* MCAM keysize 112/224/448 bits */
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u8 banks; /* Number of MCAM banks */
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u8 banks_per_entry;/* Number of keywords in key */
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u16 banksize; /* Number of MCAM entries in each bank */
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u16 total_entries; /* Total number of MCAM entries */
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u16 nixlf_offset; /* Offset of nixlf rsvd uncast entries */
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u16 pf_offset; /* Offset of PF's rsvd bcast, promisc entries */
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u16 lprio_count;
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u16 lprio_start;
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u16 hprio_count;
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u16 hprio_end;
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u16 rx_miss_act_cntr; /* Counter for RX MISS action */
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/* fields present in the generated key */
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struct npc_key_field tx_key_fields[NPC_KEY_FIELDS_MAX];
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struct npc_key_field rx_key_fields[NPC_KEY_FIELDS_MAX];
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u64 tx_features;
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u64 rx_features;
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struct list_head mcam_rules;
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};
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/* Structure for per RVU func info ie PF/VF */
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struct rvu_pfvf {
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bool npalf; /* Only one NPALF per RVU_FUNC */
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bool nixlf; /* Only one NIXLF per RVU_FUNC */
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u16 sso;
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u16 ssow;
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u16 cptlfs;
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u16 timlfs;
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u16 cpt1_lfs;
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u8 cgx_lmac;
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/* Block LF's MSIX vector info */
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struct rsrc_bmap msix; /* Bitmap for MSIX vector alloc */
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#define MSIX_BLKLF(blkaddr, lf) (((blkaddr) << 8) | ((lf) & 0xFF))
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u16 *msix_lfmap; /* Vector to block LF mapping */
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/* NPA contexts */
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struct qmem *aura_ctx;
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struct qmem *pool_ctx;
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struct qmem *npa_qints_ctx;
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unsigned long *aura_bmap;
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unsigned long *pool_bmap;
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/* NIX contexts */
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struct qmem *rq_ctx;
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struct qmem *sq_ctx;
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struct qmem *cq_ctx;
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struct qmem *rss_ctx;
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struct qmem *cq_ints_ctx;
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struct qmem *nix_qints_ctx;
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unsigned long *sq_bmap;
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unsigned long *rq_bmap;
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unsigned long *cq_bmap;
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u16 rx_chan_base;
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u16 tx_chan_base;
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u8 rx_chan_cnt; /* total number of RX channels */
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u8 tx_chan_cnt; /* total number of TX channels */
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u16 maxlen;
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u16 minlen;
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bool hw_rx_tstamp_en; /* Is rx_tstamp enabled */
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u8 mac_addr[ETH_ALEN]; /* MAC address of this PF/VF */
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u8 default_mac[ETH_ALEN]; /* MAC address from FWdata */
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/* Broadcast/Multicast/Promisc pkt replication info */
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u16 bcast_mce_idx;
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u16 mcast_mce_idx;
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u16 promisc_mce_idx;
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struct nix_mce_list bcast_mce_list;
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struct nix_mce_list mcast_mce_list;
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struct nix_mce_list promisc_mce_list;
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bool use_mce_list;
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struct rvu_npc_mcam_rule *def_ucast_rule;
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bool cgx_in_use; /* this PF/VF using CGX? */
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int cgx_users; /* number of cgx users - used only by PFs */
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int intf_mode;
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u8 nix_blkaddr; /* BLKADDR_NIX0/1 assigned to this PF */
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u8 nix_rx_intf; /* NIX0_RX/NIX1_RX interface to NPC */
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u8 nix_tx_intf; /* NIX0_TX/NIX1_TX interface to NPC */
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u8 lbkid; /* NIX0/1 lbk link ID */
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u64 lmt_base_addr; /* Preseving the pcifunc's lmtst base addr*/
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u64 lmt_map_ent_w1; /* Preseving the word1 of lmtst map table entry*/
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unsigned long flags;
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struct sdp_node_info *sdp_info;
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};
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enum rvu_pfvf_flags {
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NIXLF_INITIALIZED = 0,
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PF_SET_VF_MAC,
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PF_SET_VF_CFG,
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PF_SET_VF_TRUSTED,
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};
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#define RVU_CLEAR_VF_PERM ~GENMASK(PF_SET_VF_TRUSTED, PF_SET_VF_MAC)
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struct nix_txsch {
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struct rsrc_bmap schq;
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u8 lvl;
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#define NIX_TXSCHQ_FREE BIT_ULL(1)
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#define NIX_TXSCHQ_CFG_DONE BIT_ULL(0)
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#define TXSCH_MAP_FUNC(__pfvf_map) ((__pfvf_map) & 0xFFFF)
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#define TXSCH_MAP_FLAGS(__pfvf_map) ((__pfvf_map) >> 16)
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#define TXSCH_MAP(__func, __flags) (((__func) & 0xFFFF) | ((__flags) << 16))
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#define TXSCH_SET_FLAG(__pfvf_map, flag) ((__pfvf_map) | ((flag) << 16))
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u32 *pfvf_map;
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};
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struct nix_mark_format {
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u8 total;
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u8 in_use;
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u32 *cfg;
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};
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struct npc_pkind {
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struct rsrc_bmap rsrc;
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u32 *pfchan_map;
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};
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struct nix_flowkey {
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#define NIX_FLOW_KEY_ALG_MAX 32
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u32 flowkey[NIX_FLOW_KEY_ALG_MAX];
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int in_use;
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};
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struct nix_lso {
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u8 total;
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u8 in_use;
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};
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struct nix_txvlan {
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#define NIX_TX_VTAG_DEF_MAX 0x400
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struct rsrc_bmap rsrc;
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u16 *entry2pfvf_map;
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struct mutex rsrc_lock; /* Serialize resource alloc/free */
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};
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struct nix_ipolicer {
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struct rsrc_bmap band_prof;
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u16 *pfvf_map;
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u16 *match_id;
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u16 *ref_count;
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};
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struct nix_hw {
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int blkaddr;
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struct rvu *rvu;
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struct nix_txsch txsch[NIX_TXSCH_LVL_CNT]; /* Tx schedulers */
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struct nix_mcast mcast;
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struct nix_flowkey flowkey;
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struct nix_mark_format mark_format;
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struct nix_lso lso;
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struct nix_txvlan txvlan;
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struct nix_ipolicer *ipolicer;
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u64 *tx_credits;
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};
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/* RVU block's capabilities or functionality,
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* which vary by silicon version/skew.
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*/
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struct hw_cap {
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/* Transmit side supported functionality */
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u8 nix_tx_aggr_lvl; /* Tx link's traffic aggregation level */
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u16 nix_txsch_per_cgx_lmac; /* Max Q's transmitting to CGX LMAC */
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u16 nix_txsch_per_lbk_lmac; /* Max Q's transmitting to LBK LMAC */
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u16 nix_txsch_per_sdp_lmac; /* Max Q's transmitting to SDP LMAC */
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bool nix_fixed_txschq_mapping; /* Schq mapping fixed or flexible */
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bool nix_shaping; /* Is shaping and coloring supported */
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bool nix_shaper_toggle_wait; /* Shaping toggle needs poll/wait */
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bool nix_tx_link_bp; /* Can link backpressure TL queues ? */
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bool nix_rx_multicast; /* Rx packet replication support */
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bool nix_common_dwrr_mtu; /* Common DWRR MTU for quantum config */
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bool per_pf_mbox_regs; /* PF mbox specified in per PF registers ? */
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bool programmable_chans; /* Channels programmable ? */
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bool ipolicer;
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bool npc_hash_extract; /* Hash extract enabled ? */
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bool npc_exact_match_enabled; /* Exact match supported ? */
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};
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struct rvu_hwinfo {
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u8 total_pfs; /* MAX RVU PFs HW supports */
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u16 total_vfs; /* Max RVU VFs HW supports */
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u16 max_vfs_per_pf; /* Max VFs that can be attached to a PF */
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u8 cgx;
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u8 lmac_per_cgx;
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u16 cgx_chan_base; /* CGX base channel number */
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u16 lbk_chan_base; /* LBK base channel number */
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u16 sdp_chan_base; /* SDP base channel number */
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u16 cpt_chan_base; /* CPT base channel number */
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u8 cgx_links;
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u8 lbk_links;
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u8 sdp_links;
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u8 cpt_links; /* Number of CPT links */
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u8 npc_kpus; /* No of parser units */
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u8 npc_pkinds; /* No of port kinds */
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u8 npc_intfs; /* No of interfaces */
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u8 npc_kpu_entries; /* No of KPU entries */
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u16 npc_counters; /* No of match stats counters */
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u32 lbk_bufsize; /* FIFO size supported by LBK */
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bool npc_ext_set; /* Extended register set */
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u64 npc_stat_ena; /* Match stats enable bit */
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struct hw_cap cap;
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struct rvu_block block[BLK_COUNT]; /* Block info */
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struct nix_hw *nix;
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struct rvu *rvu;
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struct npc_pkind pkind;
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struct npc_mcam mcam;
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struct npc_exact_table *table;
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};
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struct mbox_wq_info {
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struct otx2_mbox mbox;
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struct rvu_work *mbox_wrk;
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struct otx2_mbox mbox_up;
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struct rvu_work *mbox_wrk_up;
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struct workqueue_struct *mbox_wq;
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};
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struct rvu_fwdata {
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#define RVU_FWDATA_HEADER_MAGIC 0xCFDA /* Custom Firmware Data*/
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#define RVU_FWDATA_VERSION 0x0001
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u32 header_magic;
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u32 version; /* version id */
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/* MAC address */
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#define PF_MACNUM_MAX 32
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#define VF_MACNUM_MAX 256
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u64 pf_macs[PF_MACNUM_MAX];
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u64 vf_macs[VF_MACNUM_MAX];
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u64 sclk;
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u64 rclk;
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u64 mcam_addr;
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u64 mcam_sz;
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u64 msixtr_base;
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u32 ptp_ext_clk_rate;
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u32 ptp_ext_tstamp;
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#define FWDATA_RESERVED_MEM 1022
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u64 reserved[FWDATA_RESERVED_MEM];
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#define CGX_MAX 5
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#define CGX_LMACS_MAX 4
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struct cgx_lmac_fwdata_s cgx_fw_data[CGX_MAX][CGX_LMACS_MAX];
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/* Do not add new fields below this line */
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};
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struct ptp;
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/* KPU profile adapter structure gathering all KPU configuration data and abstracting out the
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* source where it came from.
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*/
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struct npc_kpu_profile_adapter {
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const char *name;
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u64 version;
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const struct npc_lt_def_cfg *lt_def;
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const struct npc_kpu_profile_action *ikpu; /* array[pkinds] */
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const struct npc_kpu_profile *kpu; /* array[kpus] */
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struct npc_mcam_kex *mkex;
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struct npc_mcam_kex_hash *mkex_hash;
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bool custom;
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size_t pkinds;
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size_t kpus;
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};
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#define RVU_SWITCH_LBK_CHAN 63
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struct rvu_switch {
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struct mutex switch_lock; /* Serialize flow installation */
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u32 used_entries;
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u16 *entry2pcifunc;
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u16 mode;
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u16 start_entry;
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};
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struct rvu {
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void __iomem *afreg_base;
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void __iomem *pfreg_base;
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struct pci_dev *pdev;
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struct device *dev;
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struct rvu_hwinfo *hw;
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struct rvu_pfvf *pf;
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struct rvu_pfvf *hwvf;
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struct mutex rsrc_lock; /* Serialize resource alloc/free */
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int vfs; /* Number of VFs attached to RVU */
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int nix_blkaddr[MAX_NIX_BLKS];
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/* Mbox */
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struct mbox_wq_info afpf_wq_info;
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struct mbox_wq_info afvf_wq_info;
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/* PF FLR */
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struct rvu_work *flr_wrk;
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struct workqueue_struct *flr_wq;
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struct mutex flr_lock; /* Serialize FLRs */
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/* MSI-X */
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u16 num_vec;
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char *irq_name;
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bool *irq_allocated;
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dma_addr_t msix_base_iova;
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u64 msixtr_base_phy; /* Register reset value */
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/* CGX */
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#define PF_CGXMAP_BASE 1 /* PF 0 is reserved for RVU PF */
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u16 cgx_mapped_vfs; /* maximum CGX mapped VFs */
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u8 cgx_mapped_pfs;
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u8 cgx_cnt_max; /* CGX port count max */
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u8 *pf2cgxlmac_map; /* pf to cgx_lmac map */
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u16 *cgxlmac2pf_map; /* bitmap of mapped pfs for
|
|
* every cgx lmac port
|
|
*/
|
|
unsigned long pf_notify_bmap; /* Flags for PF notification */
|
|
void **cgx_idmap; /* cgx id to cgx data map table */
|
|
struct work_struct cgx_evh_work;
|
|
struct workqueue_struct *cgx_evh_wq;
|
|
spinlock_t cgx_evq_lock; /* cgx event queue lock */
|
|
struct list_head cgx_evq_head; /* cgx event queue head */
|
|
struct mutex cgx_cfg_lock; /* serialize cgx configuration */
|
|
|
|
char mkex_pfl_name[MKEX_NAME_LEN]; /* Configured MKEX profile name */
|
|
char kpu_pfl_name[KPU_NAME_LEN]; /* Configured KPU profile name */
|
|
|
|
/* Firmware data */
|
|
struct rvu_fwdata *fwdata;
|
|
void *kpu_fwdata;
|
|
size_t kpu_fwdata_sz;
|
|
void __iomem *kpu_prfl_addr;
|
|
|
|
/* NPC KPU data */
|
|
struct npc_kpu_profile_adapter kpu;
|
|
|
|
struct ptp *ptp;
|
|
|
|
int mcs_blk_cnt;
|
|
|
|
#ifdef CONFIG_DEBUG_FS
|
|
struct rvu_debugfs rvu_dbg;
|
|
#endif
|
|
struct rvu_devlink *rvu_dl;
|
|
|
|
/* RVU switch implementation over NPC with DMAC rules */
|
|
struct rvu_switch rswitch;
|
|
|
|
struct work_struct mcs_intr_work;
|
|
struct workqueue_struct *mcs_intr_wq;
|
|
struct list_head mcs_intrq_head;
|
|
/* mcs interrupt queue lock */
|
|
spinlock_t mcs_intrq_lock;
|
|
};
|
|
|
|
static inline void rvu_write64(struct rvu *rvu, u64 block, u64 offset, u64 val)
|
|
{
|
|
writeq(val, rvu->afreg_base + ((block << 28) | offset));
|
|
}
|
|
|
|
static inline u64 rvu_read64(struct rvu *rvu, u64 block, u64 offset)
|
|
{
|
|
return readq(rvu->afreg_base + ((block << 28) | offset));
|
|
}
|
|
|
|
static inline void rvupf_write64(struct rvu *rvu, u64 offset, u64 val)
|
|
{
|
|
writeq(val, rvu->pfreg_base + offset);
|
|
}
|
|
|
|
static inline u64 rvupf_read64(struct rvu *rvu, u64 offset)
|
|
{
|
|
return readq(rvu->pfreg_base + offset);
|
|
}
|
|
|
|
/* Silicon revisions */
|
|
static inline bool is_rvu_pre_96xx_C0(struct rvu *rvu)
|
|
{
|
|
struct pci_dev *pdev = rvu->pdev;
|
|
/* 96XX A0/B0, 95XX A0/A1/B0 chips */
|
|
return ((pdev->revision == 0x00) || (pdev->revision == 0x01) ||
|
|
(pdev->revision == 0x10) || (pdev->revision == 0x11) ||
|
|
(pdev->revision == 0x14));
|
|
}
|
|
|
|
static inline bool is_rvu_96xx_A0(struct rvu *rvu)
|
|
{
|
|
struct pci_dev *pdev = rvu->pdev;
|
|
|
|
return (pdev->revision == 0x00);
|
|
}
|
|
|
|
static inline bool is_rvu_96xx_B0(struct rvu *rvu)
|
|
{
|
|
struct pci_dev *pdev = rvu->pdev;
|
|
|
|
return (pdev->revision == 0x00) || (pdev->revision == 0x01);
|
|
}
|
|
|
|
static inline bool is_rvu_95xx_A0(struct rvu *rvu)
|
|
{
|
|
struct pci_dev *pdev = rvu->pdev;
|
|
|
|
return (pdev->revision == 0x10) || (pdev->revision == 0x11);
|
|
}
|
|
|
|
/* REVID for PCIe devices.
|
|
* Bits 0..1: minor pass, bit 3..2: major pass
|
|
* bits 7..4: midr id
|
|
*/
|
|
#define PCI_REVISION_ID_96XX 0x00
|
|
#define PCI_REVISION_ID_95XX 0x10
|
|
#define PCI_REVISION_ID_95XXN 0x20
|
|
#define PCI_REVISION_ID_98XX 0x30
|
|
#define PCI_REVISION_ID_95XXMM 0x40
|
|
#define PCI_REVISION_ID_95XXO 0xE0
|
|
|
|
static inline bool is_rvu_otx2(struct rvu *rvu)
|
|
{
|
|
struct pci_dev *pdev = rvu->pdev;
|
|
|
|
u8 midr = pdev->revision & 0xF0;
|
|
|
|
return (midr == PCI_REVISION_ID_96XX || midr == PCI_REVISION_ID_95XX ||
|
|
midr == PCI_REVISION_ID_95XXN || midr == PCI_REVISION_ID_98XX ||
|
|
midr == PCI_REVISION_ID_95XXMM || midr == PCI_REVISION_ID_95XXO);
|
|
}
|
|
|
|
static inline bool is_rvu_npc_hash_extract_en(struct rvu *rvu)
|
|
{
|
|
u64 npc_const3;
|
|
|
|
npc_const3 = rvu_read64(rvu, BLKADDR_NPC, NPC_AF_CONST3);
|
|
if (!(npc_const3 & BIT_ULL(62)))
|
|
return false;
|
|
|
|
return true;
|
|
}
|
|
|
|
static inline u16 rvu_nix_chan_cgx(struct rvu *rvu, u8 cgxid,
|
|
u8 lmacid, u8 chan)
|
|
{
|
|
u64 nix_const = rvu_read64(rvu, BLKADDR_NIX0, NIX_AF_CONST);
|
|
u16 cgx_chans = nix_const & 0xFFULL;
|
|
struct rvu_hwinfo *hw = rvu->hw;
|
|
|
|
if (!hw->cap.programmable_chans)
|
|
return NIX_CHAN_CGX_LMAC_CHX(cgxid, lmacid, chan);
|
|
|
|
return rvu->hw->cgx_chan_base +
|
|
(cgxid * hw->lmac_per_cgx + lmacid) * cgx_chans + chan;
|
|
}
|
|
|
|
static inline u16 rvu_nix_chan_lbk(struct rvu *rvu, u8 lbkid,
|
|
u8 chan)
|
|
{
|
|
u64 nix_const = rvu_read64(rvu, BLKADDR_NIX0, NIX_AF_CONST);
|
|
u16 lbk_chans = (nix_const >> 16) & 0xFFULL;
|
|
struct rvu_hwinfo *hw = rvu->hw;
|
|
|
|
if (!hw->cap.programmable_chans)
|
|
return NIX_CHAN_LBK_CHX(lbkid, chan);
|
|
|
|
return rvu->hw->lbk_chan_base + lbkid * lbk_chans + chan;
|
|
}
|
|
|
|
static inline u16 rvu_nix_chan_sdp(struct rvu *rvu, u8 chan)
|
|
{
|
|
struct rvu_hwinfo *hw = rvu->hw;
|
|
|
|
if (!hw->cap.programmable_chans)
|
|
return NIX_CHAN_SDP_CHX(chan);
|
|
|
|
return hw->sdp_chan_base + chan;
|
|
}
|
|
|
|
static inline u16 rvu_nix_chan_cpt(struct rvu *rvu, u8 chan)
|
|
{
|
|
return rvu->hw->cpt_chan_base + chan;
|
|
}
|
|
|
|
static inline bool is_rvu_supports_nix1(struct rvu *rvu)
|
|
{
|
|
struct pci_dev *pdev = rvu->pdev;
|
|
|
|
if (pdev->subsystem_device == PCI_SUBSYS_DEVID_98XX)
|
|
return true;
|
|
|
|
return false;
|
|
}
|
|
|
|
/* Function Prototypes
|
|
* RVU
|
|
*/
|
|
static inline bool is_afvf(u16 pcifunc)
|
|
{
|
|
return !(pcifunc & ~RVU_PFVF_FUNC_MASK);
|
|
}
|
|
|
|
static inline bool is_vf(u16 pcifunc)
|
|
{
|
|
return !!(pcifunc & RVU_PFVF_FUNC_MASK);
|
|
}
|
|
|
|
/* check if PF_FUNC is AF */
|
|
static inline bool is_pffunc_af(u16 pcifunc)
|
|
{
|
|
return !pcifunc;
|
|
}
|
|
|
|
static inline bool is_rvu_fwdata_valid(struct rvu *rvu)
|
|
{
|
|
return (rvu->fwdata->header_magic == RVU_FWDATA_HEADER_MAGIC) &&
|
|
(rvu->fwdata->version == RVU_FWDATA_VERSION);
|
|
}
|
|
|
|
int rvu_alloc_bitmap(struct rsrc_bmap *rsrc);
|
|
void rvu_free_bitmap(struct rsrc_bmap *rsrc);
|
|
int rvu_alloc_rsrc(struct rsrc_bmap *rsrc);
|
|
void rvu_free_rsrc(struct rsrc_bmap *rsrc, int id);
|
|
bool is_rsrc_free(struct rsrc_bmap *rsrc, int id);
|
|
int rvu_rsrc_free_count(struct rsrc_bmap *rsrc);
|
|
int rvu_alloc_rsrc_contig(struct rsrc_bmap *rsrc, int nrsrc);
|
|
bool rvu_rsrc_check_contig(struct rsrc_bmap *rsrc, int nrsrc);
|
|
u16 rvu_get_rsrc_mapcount(struct rvu_pfvf *pfvf, int blkaddr);
|
|
int rvu_get_pf(u16 pcifunc);
|
|
struct rvu_pfvf *rvu_get_pfvf(struct rvu *rvu, int pcifunc);
|
|
void rvu_get_pf_numvfs(struct rvu *rvu, int pf, int *numvfs, int *hwvf);
|
|
bool is_block_implemented(struct rvu_hwinfo *hw, int blkaddr);
|
|
bool is_pffunc_map_valid(struct rvu *rvu, u16 pcifunc, int blktype);
|
|
int rvu_get_lf(struct rvu *rvu, struct rvu_block *block, u16 pcifunc, u16 slot);
|
|
int rvu_lf_reset(struct rvu *rvu, struct rvu_block *block, int lf);
|
|
int rvu_get_blkaddr(struct rvu *rvu, int blktype, u16 pcifunc);
|
|
int rvu_poll_reg(struct rvu *rvu, u64 block, u64 offset, u64 mask, bool zero);
|
|
int rvu_get_num_lbk_chans(void);
|
|
int rvu_get_blkaddr_from_slot(struct rvu *rvu, int blktype, u16 pcifunc,
|
|
u16 global_slot, u16 *slot_in_block);
|
|
|
|
/* RVU HW reg validation */
|
|
enum regmap_block {
|
|
TXSCHQ_HWREGMAP = 0,
|
|
MAX_HWREGMAP,
|
|
};
|
|
|
|
bool rvu_check_valid_reg(int regmap, int regblk, u64 reg);
|
|
|
|
/* NPA/NIX AQ APIs */
|
|
int rvu_aq_alloc(struct rvu *rvu, struct admin_queue **ad_queue,
|
|
int qsize, int inst_size, int res_size);
|
|
void rvu_aq_free(struct rvu *rvu, struct admin_queue *aq);
|
|
|
|
/* SDP APIs */
|
|
int rvu_sdp_init(struct rvu *rvu);
|
|
bool is_sdp_pfvf(u16 pcifunc);
|
|
bool is_sdp_pf(u16 pcifunc);
|
|
bool is_sdp_vf(u16 pcifunc);
|
|
|
|
/* CGX APIs */
|
|
static inline bool is_pf_cgxmapped(struct rvu *rvu, u8 pf)
|
|
{
|
|
return (pf >= PF_CGXMAP_BASE && pf <= rvu->cgx_mapped_pfs) &&
|
|
!is_sdp_pf(pf << RVU_PFVF_PF_SHIFT);
|
|
}
|
|
|
|
static inline void rvu_get_cgx_lmac_id(u8 map, u8 *cgx_id, u8 *lmac_id)
|
|
{
|
|
*cgx_id = (map >> 4) & 0xF;
|
|
*lmac_id = (map & 0xF);
|
|
}
|
|
|
|
static inline bool is_cgx_vf(struct rvu *rvu, u16 pcifunc)
|
|
{
|
|
return ((pcifunc & RVU_PFVF_FUNC_MASK) &&
|
|
is_pf_cgxmapped(rvu, rvu_get_pf(pcifunc)));
|
|
}
|
|
|
|
#define M(_name, _id, fn_name, req, rsp) \
|
|
int rvu_mbox_handler_ ## fn_name(struct rvu *, struct req *, struct rsp *);
|
|
MBOX_MESSAGES
|
|
#undef M
|
|
|
|
int rvu_cgx_init(struct rvu *rvu);
|
|
int rvu_cgx_exit(struct rvu *rvu);
|
|
void *rvu_cgx_pdata(u8 cgx_id, struct rvu *rvu);
|
|
int rvu_cgx_config_rxtx(struct rvu *rvu, u16 pcifunc, bool start);
|
|
void rvu_cgx_enadis_rx_bp(struct rvu *rvu, int pf, bool enable);
|
|
int rvu_cgx_start_stop_io(struct rvu *rvu, u16 pcifunc, bool start);
|
|
int rvu_cgx_nix_cuml_stats(struct rvu *rvu, void *cgxd, int lmac_id, int index,
|
|
int rxtxflag, u64 *stat);
|
|
void rvu_cgx_disable_dmac_entries(struct rvu *rvu, u16 pcifunc);
|
|
|
|
/* NPA APIs */
|
|
int rvu_npa_init(struct rvu *rvu);
|
|
void rvu_npa_freemem(struct rvu *rvu);
|
|
void rvu_npa_lf_teardown(struct rvu *rvu, u16 pcifunc, int npalf);
|
|
int rvu_npa_aq_enq_inst(struct rvu *rvu, struct npa_aq_enq_req *req,
|
|
struct npa_aq_enq_rsp *rsp);
|
|
|
|
/* NIX APIs */
|
|
bool is_nixlf_attached(struct rvu *rvu, u16 pcifunc);
|
|
int rvu_nix_init(struct rvu *rvu);
|
|
int rvu_nix_reserve_mark_format(struct rvu *rvu, struct nix_hw *nix_hw,
|
|
int blkaddr, u32 cfg);
|
|
void rvu_nix_freemem(struct rvu *rvu);
|
|
int rvu_get_nixlf_count(struct rvu *rvu);
|
|
void rvu_nix_lf_teardown(struct rvu *rvu, u16 pcifunc, int blkaddr, int npalf);
|
|
int nix_get_nixlf(struct rvu *rvu, u16 pcifunc, int *nixlf, int *nix_blkaddr);
|
|
int nix_update_mce_list(struct rvu *rvu, u16 pcifunc,
|
|
struct nix_mce_list *mce_list,
|
|
int mce_idx, int mcam_index, bool add);
|
|
void nix_get_mce_list(struct rvu *rvu, u16 pcifunc, int type,
|
|
struct nix_mce_list **mce_list, int *mce_idx);
|
|
struct nix_hw *get_nix_hw(struct rvu_hwinfo *hw, int blkaddr);
|
|
int rvu_get_next_nix_blkaddr(struct rvu *rvu, int blkaddr);
|
|
void rvu_nix_reset_mac(struct rvu_pfvf *pfvf, int pcifunc);
|
|
int nix_get_struct_ptrs(struct rvu *rvu, u16 pcifunc,
|
|
struct nix_hw **nix_hw, int *blkaddr);
|
|
int rvu_nix_setup_ratelimit_aggr(struct rvu *rvu, u16 pcifunc,
|
|
u16 rq_idx, u16 match_id);
|
|
int nix_aq_context_read(struct rvu *rvu, struct nix_hw *nix_hw,
|
|
struct nix_cn10k_aq_enq_req *aq_req,
|
|
struct nix_cn10k_aq_enq_rsp *aq_rsp,
|
|
u16 pcifunc, u8 ctype, u32 qidx);
|
|
int rvu_get_nix_blkaddr(struct rvu *rvu, u16 pcifunc);
|
|
u32 convert_dwrr_mtu_to_bytes(u8 dwrr_mtu);
|
|
u32 convert_bytes_to_dwrr_mtu(u32 bytes);
|
|
|
|
/* NPC APIs */
|
|
void rvu_npc_freemem(struct rvu *rvu);
|
|
int rvu_npc_get_pkind(struct rvu *rvu, u16 pf);
|
|
void rvu_npc_set_pkind(struct rvu *rvu, int pkind, struct rvu_pfvf *pfvf);
|
|
int npc_config_ts_kpuaction(struct rvu *rvu, int pf, u16 pcifunc, bool en);
|
|
void rvu_npc_install_ucast_entry(struct rvu *rvu, u16 pcifunc,
|
|
int nixlf, u64 chan, u8 *mac_addr);
|
|
void rvu_npc_install_promisc_entry(struct rvu *rvu, u16 pcifunc,
|
|
int nixlf, u64 chan, u8 chan_cnt);
|
|
void rvu_npc_enable_promisc_entry(struct rvu *rvu, u16 pcifunc, int nixlf,
|
|
bool enable);
|
|
void rvu_npc_install_bcast_match_entry(struct rvu *rvu, u16 pcifunc,
|
|
int nixlf, u64 chan);
|
|
void rvu_npc_enable_bcast_entry(struct rvu *rvu, u16 pcifunc, int nixlf,
|
|
bool enable);
|
|
void rvu_npc_install_allmulti_entry(struct rvu *rvu, u16 pcifunc, int nixlf,
|
|
u64 chan);
|
|
void rvu_npc_enable_allmulti_entry(struct rvu *rvu, u16 pcifunc, int nixlf,
|
|
bool enable);
|
|
|
|
void npc_enadis_default_mce_entry(struct rvu *rvu, u16 pcifunc,
|
|
int nixlf, int type, bool enable);
|
|
void rvu_npc_disable_mcam_entries(struct rvu *rvu, u16 pcifunc, int nixlf);
|
|
bool rvu_npc_enable_mcam_by_entry_index(struct rvu *rvu, int entry, int intf, bool enable);
|
|
void rvu_npc_free_mcam_entries(struct rvu *rvu, u16 pcifunc, int nixlf);
|
|
void rvu_npc_disable_default_entries(struct rvu *rvu, u16 pcifunc, int nixlf);
|
|
void rvu_npc_enable_default_entries(struct rvu *rvu, u16 pcifunc, int nixlf);
|
|
void rvu_npc_update_flowkey_alg_idx(struct rvu *rvu, u16 pcifunc, int nixlf,
|
|
int group, int alg_idx, int mcam_index);
|
|
|
|
void rvu_npc_get_mcam_entry_alloc_info(struct rvu *rvu, u16 pcifunc,
|
|
int blkaddr, int *alloc_cnt,
|
|
int *enable_cnt);
|
|
void rvu_npc_get_mcam_counter_alloc_info(struct rvu *rvu, u16 pcifunc,
|
|
int blkaddr, int *alloc_cnt,
|
|
int *enable_cnt);
|
|
bool is_npc_intf_tx(u8 intf);
|
|
bool is_npc_intf_rx(u8 intf);
|
|
bool is_npc_interface_valid(struct rvu *rvu, u8 intf);
|
|
int rvu_npc_get_tx_nibble_cfg(struct rvu *rvu, u64 nibble_ena);
|
|
int npc_flow_steering_init(struct rvu *rvu, int blkaddr);
|
|
const char *npc_get_field_name(u8 hdr);
|
|
int npc_get_bank(struct npc_mcam *mcam, int index);
|
|
void npc_mcam_enable_flows(struct rvu *rvu, u16 target);
|
|
void npc_mcam_disable_flows(struct rvu *rvu, u16 target);
|
|
void npc_enable_mcam_entry(struct rvu *rvu, struct npc_mcam *mcam,
|
|
int blkaddr, int index, bool enable);
|
|
void npc_read_mcam_entry(struct rvu *rvu, struct npc_mcam *mcam,
|
|
int blkaddr, u16 src, struct mcam_entry *entry,
|
|
u8 *intf, u8 *ena);
|
|
bool is_cgx_config_permitted(struct rvu *rvu, u16 pcifunc);
|
|
bool is_mac_feature_supported(struct rvu *rvu, int pf, int feature);
|
|
u32 rvu_cgx_get_fifolen(struct rvu *rvu);
|
|
void *rvu_first_cgx_pdata(struct rvu *rvu);
|
|
int cgxlmac_to_pf(struct rvu *rvu, int cgx_id, int lmac_id);
|
|
int rvu_cgx_config_tx(void *cgxd, int lmac_id, bool enable);
|
|
int rvu_cgx_prio_flow_ctrl_cfg(struct rvu *rvu, u16 pcifunc, u8 tx_pause, u8 rx_pause,
|
|
u16 pfc_en);
|
|
int rvu_cgx_cfg_pause_frm(struct rvu *rvu, u16 pcifunc, u8 tx_pause, u8 rx_pause);
|
|
u32 rvu_cgx_get_lmac_fifolen(struct rvu *rvu, int cgx, int lmac);
|
|
int npc_get_nixlf_mcam_index(struct npc_mcam *mcam, u16 pcifunc, int nixlf,
|
|
int type);
|
|
bool is_mcam_entry_enabled(struct rvu *rvu, struct npc_mcam *mcam, int blkaddr,
|
|
int index);
|
|
int rvu_npc_init(struct rvu *rvu);
|
|
int npc_install_mcam_drop_rule(struct rvu *rvu, int mcam_idx, u16 *counter_idx,
|
|
u64 chan_val, u64 chan_mask, u64 exact_val, u64 exact_mask,
|
|
u64 bcast_mcast_val, u64 bcast_mcast_mask);
|
|
void npc_mcam_rsrcs_reserve(struct rvu *rvu, int blkaddr, int entry_idx);
|
|
bool npc_is_feature_supported(struct rvu *rvu, u64 features, u8 intf);
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/* CPT APIs */
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int rvu_cpt_register_interrupts(struct rvu *rvu);
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void rvu_cpt_unregister_interrupts(struct rvu *rvu);
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int rvu_cpt_lf_teardown(struct rvu *rvu, u16 pcifunc, int blkaddr, int lf,
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int slot);
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int rvu_cpt_ctx_flush(struct rvu *rvu, u16 pcifunc);
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#define NDC_AF_BANK_MASK GENMASK_ULL(7, 0)
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#define NDC_AF_BANK_LINE_MASK GENMASK_ULL(31, 16)
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/* CN10K RVU */
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int rvu_set_channels_base(struct rvu *rvu);
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void rvu_program_channels(struct rvu *rvu);
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/* CN10K RVU - LMT*/
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void rvu_reset_lmt_map_tbl(struct rvu *rvu, u16 pcifunc);
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#ifdef CONFIG_DEBUG_FS
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void rvu_dbg_init(struct rvu *rvu);
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void rvu_dbg_exit(struct rvu *rvu);
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#else
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static inline void rvu_dbg_init(struct rvu *rvu) {}
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static inline void rvu_dbg_exit(struct rvu *rvu) {}
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#endif
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int rvu_ndc_fix_locked_cacheline(struct rvu *rvu, int blkaddr);
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/* RVU Switch */
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void rvu_switch_enable(struct rvu *rvu);
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void rvu_switch_disable(struct rvu *rvu);
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void rvu_switch_update_rules(struct rvu *rvu, u16 pcifunc);
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int rvu_npc_set_parse_mode(struct rvu *rvu, u16 pcifunc, u64 mode, u8 dir,
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u64 pkind, u8 var_len_off, u8 var_len_off_mask,
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u8 shift_dir);
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int rvu_get_hwvf(struct rvu *rvu, int pcifunc);
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/* CN10K MCS */
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int rvu_mcs_init(struct rvu *rvu);
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int rvu_mcs_flr_handler(struct rvu *rvu, u16 pcifunc);
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void rvu_mcs_ptp_cfg(struct rvu *rvu, u8 rpm_id, u8 lmac_id, bool ena);
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void rvu_mcs_exit(struct rvu *rvu);
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#endif /* RVU_H */
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