232 lines
7.4 KiB
C
232 lines
7.4 KiB
C
/* SPDX-License-Identifier: GPL-2.0+ */
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/* Copyright (c) 2016-2017 Hisilicon Limited. */
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#ifndef __HCLGE_ERR_H
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#define __HCLGE_ERR_H
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#include "hclge_main.h"
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#include "hnae3.h"
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#define HCLGE_MPF_RAS_INT_MIN_BD_NUM 10
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#define HCLGE_PF_RAS_INT_MIN_BD_NUM 4
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#define HCLGE_MPF_MSIX_INT_MIN_BD_NUM 10
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#define HCLGE_PF_MSIX_INT_MIN_BD_NUM 4
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#define HCLGE_RAS_PF_OTHER_INT_STS_REG 0x20B00
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#define HCLGE_RAS_REG_NFE_MASK 0xFF00
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#define HCLGE_RAS_REG_ROCEE_ERR_MASK 0x3000000
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#define HCLGE_RAS_REG_ERR_MASK \
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(HCLGE_RAS_REG_NFE_MASK | HCLGE_RAS_REG_ROCEE_ERR_MASK)
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#define HCLGE_VECTOR0_REG_MSIX_MASK 0x1FF00
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#define HCLGE_IMP_TCM_ECC_ERR_INT_EN 0xFFFF0000
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#define HCLGE_IMP_TCM_ECC_ERR_INT_EN_MASK 0xFFFF0000
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#define HCLGE_IMP_ITCM4_ECC_ERR_INT_EN 0x300
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#define HCLGE_IMP_ITCM4_ECC_ERR_INT_EN_MASK 0x300
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#define HCLGE_CMDQ_NIC_ECC_ERR_INT_EN 0xFFFF
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#define HCLGE_CMDQ_NIC_ECC_ERR_INT_EN_MASK 0xFFFF
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#define HCLGE_CMDQ_ROCEE_ECC_ERR_INT_EN 0xFFFF0000
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#define HCLGE_CMDQ_ROCEE_ECC_ERR_INT_EN_MASK 0xFFFF0000
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#define HCLGE_IMP_RD_POISON_ERR_INT_EN 0x0100
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#define HCLGE_IMP_RD_POISON_ERR_INT_EN_MASK 0x0100
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#define HCLGE_TQP_ECC_ERR_INT_EN 0x0FFF
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#define HCLGE_TQP_ECC_ERR_INT_EN_MASK 0x0FFF
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#define HCLGE_MSIX_SRAM_ECC_ERR_INT_EN_MASK 0x0F000000
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#define HCLGE_MSIX_SRAM_ECC_ERR_INT_EN 0x0F000000
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#define HCLGE_IGU_ERR_INT_EN 0x0000000F
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#define HCLGE_IGU_ERR_INT_TYPE 0x00000660
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#define HCLGE_IGU_ERR_INT_EN_MASK 0x000F
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#define HCLGE_IGU_TNL_ERR_INT_EN 0x0002AABF
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#define HCLGE_IGU_TNL_ERR_INT_EN_MASK 0x003F
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#define HCLGE_PPP_MPF_ECC_ERR_INT0_EN 0xFFFFFFFF
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#define HCLGE_PPP_MPF_ECC_ERR_INT0_EN_MASK 0xFFFFFFFF
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#define HCLGE_PPP_MPF_ECC_ERR_INT1_EN 0xFFFFFFFF
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#define HCLGE_PPP_MPF_ECC_ERR_INT1_EN_MASK 0xFFFFFFFF
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#define HCLGE_PPP_PF_ERR_INT_EN 0x0003
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#define HCLGE_PPP_PF_ERR_INT_EN_MASK 0x0003
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#define HCLGE_PPP_MPF_ECC_ERR_INT2_EN 0x003F
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#define HCLGE_PPP_MPF_ECC_ERR_INT2_EN_MASK 0x003F
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#define HCLGE_PPP_MPF_ECC_ERR_INT3_EN 0x003F
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#define HCLGE_PPP_MPF_ECC_ERR_INT3_EN_MASK 0x003F
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#define HCLGE_TM_SCH_ECC_ERR_INT_EN 0x3
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#define HCLGE_TM_QCN_ERR_INT_TYPE 0x29
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#define HCLGE_TM_QCN_FIFO_INT_EN 0xFFFF00
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#define HCLGE_TM_QCN_MEM_ERR_INT_EN 0xFFFFFF
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#define HCLGE_NCSI_ERR_INT_EN 0x3
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#define HCLGE_NCSI_ERR_INT_TYPE 0x9
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#define HCLGE_MAC_COMMON_ERR_INT_EN 0x107FF
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#define HCLGE_MAC_COMMON_ERR_INT_EN_MASK 0x107FF
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#define HCLGE_MAC_TNL_INT_EN GENMASK(9, 0)
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#define HCLGE_MAC_TNL_INT_EN_MASK GENMASK(9, 0)
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#define HCLGE_MAC_TNL_INT_CLR GENMASK(9, 0)
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#define HCLGE_PPU_MPF_ABNORMAL_INT0_EN GENMASK(31, 0)
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#define HCLGE_PPU_MPF_ABNORMAL_INT0_EN_MASK GENMASK(31, 0)
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#define HCLGE_PPU_MPF_ABNORMAL_INT1_EN GENMASK(31, 0)
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#define HCLGE_PPU_MPF_ABNORMAL_INT1_EN_MASK GENMASK(31, 0)
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#define HCLGE_PPU_MPF_ABNORMAL_INT2_EN 0x3FFF3FFF
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#define HCLGE_PPU_MPF_ABNORMAL_INT2_EN_MASK 0x3FFF3FFF
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#define HCLGE_PPU_MPF_ABNORMAL_INT2_EN2 0xB
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#define HCLGE_PPU_MPF_ABNORMAL_INT2_EN2_MASK 0xB
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#define HCLGE_PPU_MPF_ABNORMAL_INT3_EN GENMASK(7, 0)
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#define HCLGE_PPU_MPF_ABNORMAL_INT3_EN_MASK GENMASK(23, 16)
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#define HCLGE_PPU_PF_ABNORMAL_INT_EN GENMASK(5, 0)
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#define HCLGE_PPU_PF_ABNORMAL_INT_EN_MASK GENMASK(5, 0)
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#define HCLGE_SSU_1BIT_ECC_ERR_INT_EN GENMASK(31, 0)
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#define HCLGE_SSU_1BIT_ECC_ERR_INT_EN_MASK GENMASK(31, 0)
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#define HCLGE_SSU_MULTI_BIT_ECC_ERR_INT_EN GENMASK(31, 0)
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#define HCLGE_SSU_MULTI_BIT_ECC_ERR_INT_EN_MASK GENMASK(31, 0)
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#define HCLGE_SSU_BIT32_ECC_ERR_INT_EN 0x0101
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#define HCLGE_SSU_BIT32_ECC_ERR_INT_EN_MASK 0x0101
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#define HCLGE_SSU_COMMON_INT_EN GENMASK(9, 0)
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#define HCLGE_SSU_COMMON_INT_EN_MASK GENMASK(9, 0)
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#define HCLGE_SSU_PORT_BASED_ERR_INT_EN 0x0BFF
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#define HCLGE_SSU_PORT_BASED_ERR_INT_EN_MASK 0x0BFF0000
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#define HCLGE_SSU_FIFO_OVERFLOW_ERR_INT_EN GENMASK(23, 0)
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#define HCLGE_SSU_FIFO_OVERFLOW_ERR_INT_EN_MASK GENMASK(23, 0)
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#define HCLGE_SSU_COMMON_ERR_INT_MASK GENMASK(9, 0)
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#define HCLGE_SSU_PORT_INT_MSIX_MASK 0x7BFF
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#define HCLGE_IGU_INT_MASK GENMASK(3, 0)
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#define HCLGE_IGU_EGU_TNL_INT_MASK GENMASK(5, 0)
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#define HCLGE_PPP_MPF_INT_ST3_MASK GENMASK(5, 0)
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#define HCLGE_PPU_MPF_INT_ST3_MASK GENMASK(7, 0)
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#define HCLGE_PPU_MPF_INT_ST2_MSIX_MASK BIT(29)
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#define HCLGE_PPU_PF_INT_RAS_MASK 0x18
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#define HCLGE_PPU_PF_INT_MSIX_MASK 0x26
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#define HCLGE_PPU_PF_OVER_8BD_ERR_MASK 0x01
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#define HCLGE_QCN_FIFO_INT_MASK GENMASK(17, 0)
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#define HCLGE_QCN_ECC_INT_MASK GENMASK(21, 0)
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#define HCLGE_NCSI_ECC_INT_MASK GENMASK(1, 0)
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#define HCLGE_ROCEE_RAS_NFE_INT_EN 0xF
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#define HCLGE_ROCEE_RAS_CE_INT_EN 0x1
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#define HCLGE_ROCEE_RAS_NFE_INT_EN_MASK 0xF
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#define HCLGE_ROCEE_RAS_CE_INT_EN_MASK 0x1
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#define HCLGE_ROCEE_RERR_INT_MASK BIT(0)
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#define HCLGE_ROCEE_BERR_INT_MASK BIT(1)
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#define HCLGE_ROCEE_AXI_ERR_INT_MASK GENMASK(1, 0)
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#define HCLGE_ROCEE_ECC_INT_MASK BIT(2)
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#define HCLGE_ROCEE_OVF_INT_MASK BIT(3)
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#define HCLGE_ROCEE_OVF_ERR_INT_MASK 0x10000
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#define HCLGE_ROCEE_OVF_ERR_TYPE_MASK 0x3F
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#define HCLGE_DESC_DATA_MAX 8
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#define HCLGE_REG_NUM_MAX 256
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#define HCLGE_DESC_NO_DATA_LEN 8
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enum hclge_err_int_type {
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HCLGE_ERR_INT_MSIX = 0,
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HCLGE_ERR_INT_RAS_CE = 1,
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HCLGE_ERR_INT_RAS_NFE = 2,
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HCLGE_ERR_INT_RAS_FE = 3,
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};
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enum hclge_mod_name_list {
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MODULE_NONE = 0,
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MODULE_BIOS_COMMON = 1,
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MODULE_GE = 2,
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MODULE_IGU_EGU = 3,
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MODULE_LGE = 4,
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MODULE_NCSI = 5,
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MODULE_PPP = 6,
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MODULE_QCN = 7,
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MODULE_RCB_RX = 8,
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MODULE_RTC = 9,
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MODULE_SSU = 10,
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MODULE_TM = 11,
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MODULE_RCB_TX = 12,
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MODULE_TXDMA = 13,
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MODULE_MASTER = 14,
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MODULE_HIMAC = 15,
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/* add new MODULE NAME for NIC here in order */
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MODULE_ROCEE_TOP = 40,
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MODULE_ROCEE_TIMER = 41,
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MODULE_ROCEE_MDB = 42,
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MODULE_ROCEE_TSP = 43,
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MODULE_ROCEE_TRP = 44,
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MODULE_ROCEE_SCC = 45,
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MODULE_ROCEE_CAEP = 46,
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MODULE_ROCEE_GEN_AC = 47,
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MODULE_ROCEE_QMM = 48,
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MODULE_ROCEE_LSAN = 49,
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/* add new MODULE NAME for RoCEE here in order */
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};
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enum hclge_err_type_list {
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NONE_ERROR = 0,
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FIFO_ERROR = 1,
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MEMORY_ERROR = 2,
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POISON_ERROR = 3,
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MSIX_ECC_ERROR = 4,
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TQP_INT_ECC_ERROR = 5,
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PF_ABNORMAL_INT_ERROR = 6,
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MPF_ABNORMAL_INT_ERROR = 7,
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COMMON_ERROR = 8,
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PORT_ERROR = 9,
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ETS_ERROR = 10,
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NCSI_ERROR = 11,
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GLB_ERROR = 12,
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LINK_ERROR = 13,
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PTP_ERROR = 14,
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/* add new ERROR TYPE for NIC here in order */
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ROCEE_NORMAL_ERR = 40,
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ROCEE_OVF_ERR = 41,
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ROCEE_BUS_ERR = 42,
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/* add new ERROR TYPE for ROCEE here in order */
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};
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struct hclge_hw_blk {
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u32 msk;
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const char *name;
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int (*config_err_int)(struct hclge_dev *hdev, bool en);
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};
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struct hclge_hw_error {
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u32 int_msk;
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const char *msg;
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enum hnae3_reset_type reset_level;
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};
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struct hclge_hw_module_id {
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enum hclge_mod_name_list module_id;
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const char *msg;
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};
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struct hclge_hw_type_id {
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enum hclge_err_type_list type_id;
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const char *msg;
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};
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struct hclge_sum_err_info {
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u8 reset_type;
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u8 mod_num;
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u8 rsv[2];
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};
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struct hclge_mod_err_info {
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u8 mod_id;
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u8 err_num;
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u8 rsv[2];
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};
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struct hclge_type_reg_err_info {
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u8 type_id;
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u8 reg_num;
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u8 rsv[2];
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u32 hclge_reg[HCLGE_REG_NUM_MAX];
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};
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int hclge_config_mac_tnl_int(struct hclge_dev *hdev, bool en);
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int hclge_config_nic_hw_error(struct hclge_dev *hdev, bool state);
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int hclge_config_rocee_ras_interrupt(struct hclge_dev *hdev, bool en);
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void hclge_handle_all_hns_hw_errors(struct hnae3_ae_dev *ae_dev);
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bool hclge_find_error_source(struct hclge_dev *hdev);
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void hclge_handle_occurred_error(struct hclge_dev *hdev);
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pci_ers_result_t hclge_handle_hw_ras_error(struct hnae3_ae_dev *ae_dev);
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int hclge_handle_hw_msix_error(struct hclge_dev *hdev,
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unsigned long *reset_requests);
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int hclge_handle_error_info_log(struct hnae3_ae_dev *ae_dev);
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int hclge_handle_mac_tnl(struct hclge_dev *hdev);
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#endif
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