409 lines
13 KiB
C
409 lines
13 KiB
C
/*
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* Copyright 2008 Stuart Bennett
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE AUTHORS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
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* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
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* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
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* SOFTWARE.
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*/
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#ifndef __NOUVEAU_HW_H__
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#define __NOUVEAU_HW_H__
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#include "disp.h"
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#include "nvreg.h"
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#include <subdev/bios/pll.h>
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#define MASK(field) ( \
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(0xffffffff >> (31 - ((1 ? field) - (0 ? field)))) << (0 ? field))
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#define XLATE(src, srclowbit, outfield) ( \
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(((src) >> (srclowbit)) << (0 ? outfield)) & MASK(outfield))
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void NVWriteVgaSeq(struct drm_device *, int head, uint8_t index, uint8_t value);
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uint8_t NVReadVgaSeq(struct drm_device *, int head, uint8_t index);
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void NVWriteVgaGr(struct drm_device *, int head, uint8_t index, uint8_t value);
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uint8_t NVReadVgaGr(struct drm_device *, int head, uint8_t index);
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void NVSetOwner(struct drm_device *, int owner);
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void NVBlankScreen(struct drm_device *, int head, bool blank);
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int nouveau_hw_get_pllvals(struct drm_device *, enum nvbios_pll_type plltype,
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struct nvkm_pll_vals *pllvals);
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int nouveau_hw_pllvals_to_clk(struct nvkm_pll_vals *pllvals);
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int nouveau_hw_get_clock(struct drm_device *, enum nvbios_pll_type plltype);
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void nouveau_hw_save_vga_fonts(struct drm_device *, bool save);
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void nouveau_hw_save_state(struct drm_device *, int head,
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struct nv04_mode_state *state);
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void nouveau_hw_load_state(struct drm_device *, int head,
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struct nv04_mode_state *state);
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void nouveau_hw_load_state_palette(struct drm_device *, int head,
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struct nv04_mode_state *state);
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/* nouveau_calc.c */
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extern void nouveau_calc_arb(struct drm_device *, int vclk, int bpp,
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int *burst, int *lwm);
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static inline uint32_t NVReadCRTC(struct drm_device *dev,
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int head, uint32_t reg)
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{
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struct nvif_object *device = &nouveau_drm(dev)->client.device.object;
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uint32_t val;
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if (head)
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reg += NV_PCRTC0_SIZE;
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val = nvif_rd32(device, reg);
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return val;
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}
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static inline void NVWriteCRTC(struct drm_device *dev,
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int head, uint32_t reg, uint32_t val)
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{
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struct nvif_object *device = &nouveau_drm(dev)->client.device.object;
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if (head)
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reg += NV_PCRTC0_SIZE;
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nvif_wr32(device, reg, val);
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}
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static inline uint32_t NVReadRAMDAC(struct drm_device *dev,
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int head, uint32_t reg)
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{
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struct nvif_object *device = &nouveau_drm(dev)->client.device.object;
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uint32_t val;
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if (head)
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reg += NV_PRAMDAC0_SIZE;
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val = nvif_rd32(device, reg);
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return val;
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}
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static inline void NVWriteRAMDAC(struct drm_device *dev,
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int head, uint32_t reg, uint32_t val)
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{
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struct nvif_object *device = &nouveau_drm(dev)->client.device.object;
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if (head)
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reg += NV_PRAMDAC0_SIZE;
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nvif_wr32(device, reg, val);
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}
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static inline uint8_t nv_read_tmds(struct drm_device *dev,
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int or, int dl, uint8_t address)
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{
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int ramdac = (or & DCB_OUTPUT_C) >> 2;
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NVWriteRAMDAC(dev, ramdac, NV_PRAMDAC_FP_TMDS_CONTROL + dl * 8,
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NV_PRAMDAC_FP_TMDS_CONTROL_WRITE_DISABLE | address);
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return NVReadRAMDAC(dev, ramdac, NV_PRAMDAC_FP_TMDS_DATA + dl * 8);
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}
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static inline void nv_write_tmds(struct drm_device *dev,
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int or, int dl, uint8_t address,
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uint8_t data)
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{
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int ramdac = (or & DCB_OUTPUT_C) >> 2;
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NVWriteRAMDAC(dev, ramdac, NV_PRAMDAC_FP_TMDS_DATA + dl * 8, data);
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NVWriteRAMDAC(dev, ramdac, NV_PRAMDAC_FP_TMDS_CONTROL + dl * 8, address);
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}
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static inline void NVWriteVgaCrtc(struct drm_device *dev,
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int head, uint8_t index, uint8_t value)
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{
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struct nvif_object *device = &nouveau_drm(dev)->client.device.object;
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nvif_wr08(device, NV_PRMCIO_CRX__COLOR + head * NV_PRMCIO_SIZE, index);
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nvif_wr08(device, NV_PRMCIO_CR__COLOR + head * NV_PRMCIO_SIZE, value);
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}
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static inline uint8_t NVReadVgaCrtc(struct drm_device *dev,
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int head, uint8_t index)
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{
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struct nvif_object *device = &nouveau_drm(dev)->client.device.object;
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uint8_t val;
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nvif_wr08(device, NV_PRMCIO_CRX__COLOR + head * NV_PRMCIO_SIZE, index);
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val = nvif_rd08(device, NV_PRMCIO_CR__COLOR + head * NV_PRMCIO_SIZE);
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return val;
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}
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/* CR57 and CR58 are a fun pair of regs. CR57 provides an index (0-0xf) for CR58
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* I suspect they in fact do nothing, but are merely a way to carry useful
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* per-head variables around
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*
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* Known uses:
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* CR57 CR58
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* 0x00 index to the appropriate dcb entry (or 7f for inactive)
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* 0x02 dcb entry's "or" value (or 00 for inactive)
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* 0x03 bit0 set for dual link (LVDS, possibly elsewhere too)
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* 0x08 or 0x09 pxclk in MHz
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* 0x0f laptop panel info - low nibble for PEXTDEV_BOOT_0 strap
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* high nibble for xlat strap value
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*/
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static inline void
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NVWriteVgaCrtc5758(struct drm_device *dev, int head, uint8_t index, uint8_t value)
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{
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NVWriteVgaCrtc(dev, head, NV_CIO_CRE_57, index);
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NVWriteVgaCrtc(dev, head, NV_CIO_CRE_58, value);
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}
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static inline uint8_t NVReadVgaCrtc5758(struct drm_device *dev, int head, uint8_t index)
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{
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NVWriteVgaCrtc(dev, head, NV_CIO_CRE_57, index);
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return NVReadVgaCrtc(dev, head, NV_CIO_CRE_58);
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}
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static inline uint8_t NVReadPRMVIO(struct drm_device *dev,
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int head, uint32_t reg)
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{
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struct nvif_object *device = &nouveau_drm(dev)->client.device.object;
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struct nouveau_drm *drm = nouveau_drm(dev);
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uint8_t val;
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/* Only NV4x have two pvio ranges; other twoHeads cards MUST call
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* NVSetOwner for the relevant head to be programmed */
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if (head && drm->client.device.info.family == NV_DEVICE_INFO_V0_CURIE)
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reg += NV_PRMVIO_SIZE;
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val = nvif_rd08(device, reg);
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return val;
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}
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static inline void NVWritePRMVIO(struct drm_device *dev,
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int head, uint32_t reg, uint8_t value)
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{
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struct nvif_object *device = &nouveau_drm(dev)->client.device.object;
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struct nouveau_drm *drm = nouveau_drm(dev);
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/* Only NV4x have two pvio ranges; other twoHeads cards MUST call
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* NVSetOwner for the relevant head to be programmed */
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if (head && drm->client.device.info.family == NV_DEVICE_INFO_V0_CURIE)
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reg += NV_PRMVIO_SIZE;
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nvif_wr08(device, reg, value);
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}
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static inline void NVSetEnablePalette(struct drm_device *dev, int head, bool enable)
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{
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struct nvif_object *device = &nouveau_drm(dev)->client.device.object;
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nvif_rd08(device, NV_PRMCIO_INP0__COLOR + head * NV_PRMCIO_SIZE);
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nvif_wr08(device, NV_PRMCIO_ARX + head * NV_PRMCIO_SIZE, enable ? 0 : 0x20);
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}
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static inline bool NVGetEnablePalette(struct drm_device *dev, int head)
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{
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struct nvif_object *device = &nouveau_drm(dev)->client.device.object;
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nvif_rd08(device, NV_PRMCIO_INP0__COLOR + head * NV_PRMCIO_SIZE);
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return !(nvif_rd08(device, NV_PRMCIO_ARX + head * NV_PRMCIO_SIZE) & 0x20);
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}
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static inline void NVWriteVgaAttr(struct drm_device *dev,
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int head, uint8_t index, uint8_t value)
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{
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struct nvif_object *device = &nouveau_drm(dev)->client.device.object;
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if (NVGetEnablePalette(dev, head))
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index &= ~0x20;
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else
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index |= 0x20;
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nvif_rd08(device, NV_PRMCIO_INP0__COLOR + head * NV_PRMCIO_SIZE);
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nvif_wr08(device, NV_PRMCIO_ARX + head * NV_PRMCIO_SIZE, index);
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nvif_wr08(device, NV_PRMCIO_AR__WRITE + head * NV_PRMCIO_SIZE, value);
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}
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static inline uint8_t NVReadVgaAttr(struct drm_device *dev,
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int head, uint8_t index)
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{
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struct nvif_object *device = &nouveau_drm(dev)->client.device.object;
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uint8_t val;
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if (NVGetEnablePalette(dev, head))
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index &= ~0x20;
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else
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index |= 0x20;
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nvif_rd08(device, NV_PRMCIO_INP0__COLOR + head * NV_PRMCIO_SIZE);
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nvif_wr08(device, NV_PRMCIO_ARX + head * NV_PRMCIO_SIZE, index);
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val = nvif_rd08(device, NV_PRMCIO_AR__READ + head * NV_PRMCIO_SIZE);
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return val;
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}
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static inline void NVVgaSeqReset(struct drm_device *dev, int head, bool start)
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{
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NVWriteVgaSeq(dev, head, NV_VIO_SR_RESET_INDEX, start ? 0x1 : 0x3);
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}
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static inline void NVVgaProtect(struct drm_device *dev, int head, bool protect)
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{
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uint8_t seq1 = NVReadVgaSeq(dev, head, NV_VIO_SR_CLOCK_INDEX);
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if (protect) {
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NVVgaSeqReset(dev, head, true);
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NVWriteVgaSeq(dev, head, NV_VIO_SR_CLOCK_INDEX, seq1 | 0x20);
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} else {
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/* Reenable sequencer, then turn on screen */
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NVWriteVgaSeq(dev, head, NV_VIO_SR_CLOCK_INDEX, seq1 & ~0x20); /* reenable display */
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NVVgaSeqReset(dev, head, false);
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}
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NVSetEnablePalette(dev, head, protect);
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}
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static inline bool
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nv_heads_tied(struct drm_device *dev)
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{
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struct nvif_object *device = &nouveau_drm(dev)->client.device.object;
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struct nouveau_drm *drm = nouveau_drm(dev);
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if (drm->client.device.info.chipset == 0x11)
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return !!(nvif_rd32(device, NV_PBUS_DEBUG_1) & (1 << 28));
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return NVReadVgaCrtc(dev, 0, NV_CIO_CRE_44) & 0x4;
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}
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/* makes cr0-7 on the specified head read-only */
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static inline bool
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nv_lock_vga_crtc_base(struct drm_device *dev, int head, bool lock)
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{
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uint8_t cr11 = NVReadVgaCrtc(dev, head, NV_CIO_CR_VRE_INDEX);
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bool waslocked = cr11 & 0x80;
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if (lock)
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cr11 |= 0x80;
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else
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cr11 &= ~0x80;
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NVWriteVgaCrtc(dev, head, NV_CIO_CR_VRE_INDEX, cr11);
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return waslocked;
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}
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static inline void
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nv_lock_vga_crtc_shadow(struct drm_device *dev, int head, int lock)
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{
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/* shadow lock: connects 0x60?3d? regs to "real" 0x3d? regs
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* bit7: unlocks HDT, HBS, HBE, HRS, HRE, HEB
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* bit6: seems to have some effect on CR09 (double scan, VBS_9)
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* bit5: unlocks HDE
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* bit4: unlocks VDE
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* bit3: unlocks VDT, OVL, VRS, ?VRE?, VBS, VBE, LSR, EBR
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* bit2: same as bit 1 of 0x60?804
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* bit0: same as bit 0 of 0x60?804
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*/
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uint8_t cr21 = lock;
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if (lock < 0)
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/* 0xfa is generic "unlock all" mask */
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cr21 = NVReadVgaCrtc(dev, head, NV_CIO_CRE_21) | 0xfa;
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NVWriteVgaCrtc(dev, head, NV_CIO_CRE_21, cr21);
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}
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/* renders the extended crtc regs (cr19+) on all crtcs impervious:
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* immutable and unreadable
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*/
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static inline bool
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NVLockVgaCrtcs(struct drm_device *dev, bool lock)
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{
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struct nouveau_drm *drm = nouveau_drm(dev);
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bool waslocked = !NVReadVgaCrtc(dev, 0, NV_CIO_SR_LOCK_INDEX);
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NVWriteVgaCrtc(dev, 0, NV_CIO_SR_LOCK_INDEX,
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lock ? NV_CIO_SR_LOCK_VALUE : NV_CIO_SR_UNLOCK_RW_VALUE);
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/* NV11 has independently lockable extended crtcs, except when tied */
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if (drm->client.device.info.chipset == 0x11 && !nv_heads_tied(dev))
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NVWriteVgaCrtc(dev, 1, NV_CIO_SR_LOCK_INDEX,
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lock ? NV_CIO_SR_LOCK_VALUE :
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NV_CIO_SR_UNLOCK_RW_VALUE);
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return waslocked;
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}
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/* nv04 cursor max dimensions of 32x32 (A1R5G5B5) */
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#define NV04_CURSOR_SIZE 32
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/* limit nv10 cursors to 64x64 (ARGB8) (we could go to 64x255) */
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#define NV10_CURSOR_SIZE 64
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static inline int nv_cursor_width(struct drm_device *dev)
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{
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struct nouveau_drm *drm = nouveau_drm(dev);
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return drm->client.device.info.family >= NV_DEVICE_INFO_V0_CELSIUS ? NV10_CURSOR_SIZE : NV04_CURSOR_SIZE;
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}
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static inline void
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nv_fix_nv40_hw_cursor(struct drm_device *dev, int head)
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{
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/* on some nv40 (such as the "true" (in the NV_PFB_BOOT_0 sense) nv40,
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* the gf6800gt) a hardware bug requires a write to PRAMDAC_CURSOR_POS
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* for changes to the CRTC CURCTL regs to take effect, whether changing
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* the pixmap location, or just showing/hiding the cursor
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*/
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uint32_t curpos = NVReadRAMDAC(dev, head, NV_PRAMDAC_CU_START_POS);
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NVWriteRAMDAC(dev, head, NV_PRAMDAC_CU_START_POS, curpos);
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}
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static inline void
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nv_set_crtc_base(struct drm_device *dev, int head, uint32_t offset)
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{
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struct nouveau_drm *drm = nouveau_drm(dev);
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NVWriteCRTC(dev, head, NV_PCRTC_START, offset);
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if (drm->client.device.info.family == NV_DEVICE_INFO_V0_TNT) {
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/*
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* Hilarious, the 24th bit doesn't want to stick to
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* PCRTC_START...
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*/
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int cre_heb = NVReadVgaCrtc(dev, head, NV_CIO_CRE_HEB__INDEX);
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NVWriteVgaCrtc(dev, head, NV_CIO_CRE_HEB__INDEX,
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(cre_heb & ~0x40) | ((offset >> 18) & 0x40));
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}
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}
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static inline void
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nv_show_cursor(struct drm_device *dev, int head, bool show)
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{
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struct nouveau_drm *drm = nouveau_drm(dev);
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uint8_t *curctl1 =
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&nv04_display(dev)->mode_reg.crtc_reg[head].CRTC[NV_CIO_CRE_HCUR_ADDR1_INDEX];
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if (show)
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*curctl1 |= MASK(NV_CIO_CRE_HCUR_ADDR1_ENABLE);
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else
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*curctl1 &= ~MASK(NV_CIO_CRE_HCUR_ADDR1_ENABLE);
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NVWriteVgaCrtc(dev, head, NV_CIO_CRE_HCUR_ADDR1_INDEX, *curctl1);
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if (drm->client.device.info.family == NV_DEVICE_INFO_V0_CURIE)
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nv_fix_nv40_hw_cursor(dev, head);
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}
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static inline uint32_t
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nv_pitch_align(struct drm_device *dev, uint32_t width, int bpp)
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{
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struct nouveau_drm *drm = nouveau_drm(dev);
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int mask;
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if (bpp == 15)
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bpp = 16;
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if (bpp == 24)
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bpp = 8;
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/* Alignment requirements taken from the Haiku driver */
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if (drm->client.device.info.family == NV_DEVICE_INFO_V0_TNT)
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mask = 128 / bpp - 1;
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else
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mask = 512 / bpp - 1;
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return (width + mask) & ~mask;
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}
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#endif /* __NOUVEAU_HW_H__ */
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