127 lines
3.8 KiB
C
127 lines
3.8 KiB
C
/* SPDX-License-Identifier: MIT */
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/*
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* Copyright © 2022 Intel Corporation
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*/
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#ifndef __I915_REG_DEFS__
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#define __I915_REG_DEFS__
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#include <linux/bitfield.h>
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#include <linux/bits.h>
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/**
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* REG_BIT() - Prepare a u32 bit value
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* @__n: 0-based bit number
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*
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* Local wrapper for BIT() to force u32, with compile time checks.
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*
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* @return: Value with bit @__n set.
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*/
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#define REG_BIT(__n) \
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((u32)(BIT(__n) + \
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BUILD_BUG_ON_ZERO(__is_constexpr(__n) && \
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((__n) < 0 || (__n) > 31))))
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/**
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* REG_GENMASK() - Prepare a continuous u32 bitmask
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* @__high: 0-based high bit
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* @__low: 0-based low bit
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*
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* Local wrapper for GENMASK() to force u32, with compile time checks.
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*
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* @return: Continuous bitmask from @__high to @__low, inclusive.
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*/
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#define REG_GENMASK(__high, __low) \
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((u32)(GENMASK(__high, __low) + \
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BUILD_BUG_ON_ZERO(__is_constexpr(__high) && \
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__is_constexpr(__low) && \
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((__low) < 0 || (__high) > 31 || (__low) > (__high)))))
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/**
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* REG_GENMASK64() - Prepare a continuous u64 bitmask
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* @__high: 0-based high bit
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* @__low: 0-based low bit
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*
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* Local wrapper for GENMASK_ULL() to force u64, with compile time checks.
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*
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* @return: Continuous bitmask from @__high to @__low, inclusive.
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*/
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#define REG_GENMASK64(__high, __low) \
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((u64)(GENMASK_ULL(__high, __low) + \
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BUILD_BUG_ON_ZERO(__is_constexpr(__high) && \
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__is_constexpr(__low) && \
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((__low) < 0 || (__high) > 63 || (__low) > (__high)))))
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/*
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* Local integer constant expression version of is_power_of_2().
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*/
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#define IS_POWER_OF_2(__x) ((__x) && (((__x) & ((__x) - 1)) == 0))
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/**
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* REG_FIELD_PREP() - Prepare a u32 bitfield value
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* @__mask: shifted mask defining the field's length and position
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* @__val: value to put in the field
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*
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* Local copy of FIELD_PREP() to generate an integer constant expression, force
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* u32 and for consistency with REG_FIELD_GET(), REG_BIT() and REG_GENMASK().
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*
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* @return: @__val masked and shifted into the field defined by @__mask.
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*/
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#define REG_FIELD_PREP(__mask, __val) \
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((u32)((((typeof(__mask))(__val) << __bf_shf(__mask)) & (__mask)) + \
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BUILD_BUG_ON_ZERO(!__is_constexpr(__mask)) + \
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BUILD_BUG_ON_ZERO((__mask) == 0 || (__mask) > U32_MAX) + \
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BUILD_BUG_ON_ZERO(!IS_POWER_OF_2((__mask) + (1ULL << __bf_shf(__mask)))) + \
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BUILD_BUG_ON_ZERO(__builtin_choose_expr(__is_constexpr(__val), (~((__mask) >> __bf_shf(__mask)) & (__val)), 0))))
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/**
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* REG_FIELD_GET() - Extract a u32 bitfield value
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* @__mask: shifted mask defining the field's length and position
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* @__val: value to extract the bitfield value from
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*
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* Local wrapper for FIELD_GET() to force u32 and for consistency with
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* REG_FIELD_PREP(), REG_BIT() and REG_GENMASK().
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*
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* @return: Masked and shifted value of the field defined by @__mask in @__val.
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*/
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#define REG_FIELD_GET(__mask, __val) ((u32)FIELD_GET(__mask, __val))
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/**
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* REG_FIELD_GET64() - Extract a u64 bitfield value
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* @__mask: shifted mask defining the field's length and position
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* @__val: value to extract the bitfield value from
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*
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* Local wrapper for FIELD_GET() to force u64 and for consistency with
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* REG_GENMASK64().
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*
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* @return: Masked and shifted value of the field defined by @__mask in @__val.
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*/
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#define REG_FIELD_GET64(__mask, __val) ((u64)FIELD_GET(__mask, __val))
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typedef struct {
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u32 reg;
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} i915_reg_t;
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#define _MMIO(r) ((const i915_reg_t){ .reg = (r) })
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#define INVALID_MMIO_REG _MMIO(0)
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static __always_inline u32 i915_mmio_reg_offset(i915_reg_t reg)
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{
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return reg.reg;
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}
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static inline bool i915_mmio_reg_equal(i915_reg_t a, i915_reg_t b)
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{
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return i915_mmio_reg_offset(a) == i915_mmio_reg_offset(b);
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}
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static inline bool i915_mmio_reg_valid(i915_reg_t reg)
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{
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return !i915_mmio_reg_equal(reg, INVALID_MMIO_REG);
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}
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#define VLV_DISPLAY_BASE 0x180000
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#endif /* __I915_REG_DEFS__ */
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