166 lines
4.1 KiB
C
166 lines
4.1 KiB
C
/*
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* SPDX-License-Identifier: MIT
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*
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* Copyright © 2017-2018 Intel Corporation
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*/
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#ifndef __I915_PMU_H__
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#define __I915_PMU_H__
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#include <linux/hrtimer.h>
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#include <linux/perf_event.h>
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#include <linux/spinlock_types.h>
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#include <uapi/drm/i915_drm.h>
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struct drm_i915_private;
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/**
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* Non-engine events that we need to track enabled-disabled transition and
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* current state.
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*/
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enum i915_pmu_tracked_events {
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__I915_PMU_ACTUAL_FREQUENCY_ENABLED = 0,
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__I915_PMU_REQUESTED_FREQUENCY_ENABLED,
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__I915_PMU_RC6_RESIDENCY_ENABLED,
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__I915_PMU_TRACKED_EVENT_COUNT, /* count marker */
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};
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/**
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* Slots used from the sampling timer (non-engine events) with some extras for
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* convenience.
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*/
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enum {
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__I915_SAMPLE_FREQ_ACT = 0,
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__I915_SAMPLE_FREQ_REQ,
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__I915_SAMPLE_RC6,
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__I915_SAMPLE_RC6_LAST_REPORTED,
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__I915_NUM_PMU_SAMPLERS
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};
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/**
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* How many different events we track in the global PMU mask.
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*
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* It is also used to know to needed number of event reference counters.
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*/
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#define I915_PMU_MASK_BITS \
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(I915_ENGINE_SAMPLE_COUNT + __I915_PMU_TRACKED_EVENT_COUNT)
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#define I915_ENGINE_SAMPLE_COUNT (I915_SAMPLE_SEMA + 1)
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struct i915_pmu_sample {
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u64 cur;
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};
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struct i915_pmu {
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/**
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* @cpuhp: Struct used for CPU hotplug handling.
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*/
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struct {
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struct hlist_node node;
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unsigned int cpu;
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} cpuhp;
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/**
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* @base: PMU base.
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*/
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struct pmu base;
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/**
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* @closed: i915 is unregistering.
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*/
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bool closed;
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/**
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* @name: Name as registered with perf core.
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*/
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const char *name;
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/**
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* @lock: Lock protecting enable mask and ref count handling.
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*/
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spinlock_t lock;
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/**
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* @timer: Timer for internal i915 PMU sampling.
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*/
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struct hrtimer timer;
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/**
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* @enable: Bitmask of specific enabled events.
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*
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* For some events we need to track their state and do some internal
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* house keeping.
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*
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* Each engine event sampler type and event listed in enum
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* i915_pmu_tracked_events gets a bit in this field.
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*
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* Low bits are engine samplers and other events continue from there.
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*/
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u32 enable;
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/**
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* @timer_last:
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*
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* Timestmap of the previous timer invocation.
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*/
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ktime_t timer_last;
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/**
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* @enable_count: Reference counts for the enabled events.
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*
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* Array indices are mapped in the same way as bits in the @enable field
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* and they are used to control sampling on/off when multiple clients
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* are using the PMU API.
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*/
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unsigned int enable_count[I915_PMU_MASK_BITS];
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/**
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* @timer_enabled: Should the internal sampling timer be running.
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*/
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bool timer_enabled;
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/**
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* @sample: Current and previous (raw) counters for sampling events.
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*
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* These counters are updated from the i915 PMU sampling timer.
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*
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* Only global counters are held here, while the per-engine ones are in
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* struct intel_engine_cs.
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*/
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struct i915_pmu_sample sample[__I915_NUM_PMU_SAMPLERS];
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/**
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* @sleep_last: Last time GT parked for RC6 estimation.
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*/
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ktime_t sleep_last;
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/**
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* @irq_count: Number of interrupts
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*
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* Intentionally unsigned long to avoid atomics or heuristics on 32bit.
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* 4e9 interrupts are a lot and postprocessing can really deal with an
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* occasional wraparound easily. It's 32bit after all.
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*/
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unsigned long irq_count;
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/**
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* @events_attr_group: Device events attribute group.
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*/
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struct attribute_group events_attr_group;
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/**
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* @i915_attr: Memory block holding device attributes.
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*/
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void *i915_attr;
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/**
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* @pmu_attr: Memory block holding device attributes.
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*/
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void *pmu_attr;
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};
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#ifdef CONFIG_PERF_EVENTS
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int i915_pmu_init(void);
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void i915_pmu_exit(void);
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void i915_pmu_register(struct drm_i915_private *i915);
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void i915_pmu_unregister(struct drm_i915_private *i915);
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void i915_pmu_gt_parked(struct drm_i915_private *i915);
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void i915_pmu_gt_unparked(struct drm_i915_private *i915);
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#else
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static inline int i915_pmu_init(void) { return 0; }
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static inline void i915_pmu_exit(void) {}
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static inline void i915_pmu_register(struct drm_i915_private *i915) {}
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static inline void i915_pmu_unregister(struct drm_i915_private *i915) {}
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static inline void i915_pmu_gt_parked(struct drm_i915_private *i915) {}
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static inline void i915_pmu_gt_unparked(struct drm_i915_private *i915) {}
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#endif
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#endif
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