445 lines
11 KiB
C
445 lines
11 KiB
C
// SPDX-License-Identifier: GPL-2.0-only
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/* Copyright (C) 2020 Marvell. */
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#include "otx2_cpt_common.h"
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#include "otx2_cptlf.h"
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#include "rvu_reg.h"
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#define CPT_TIMER_HOLD 0x03F
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#define CPT_COUNT_HOLD 32
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static void cptlf_do_set_done_time_wait(struct otx2_cptlf_info *lf,
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int time_wait)
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{
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union otx2_cptx_lf_done_wait done_wait;
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done_wait.u = otx2_cpt_read64(lf->lfs->reg_base, BLKADDR_CPT0, lf->slot,
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OTX2_CPT_LF_DONE_WAIT);
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done_wait.s.time_wait = time_wait;
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otx2_cpt_write64(lf->lfs->reg_base, BLKADDR_CPT0, lf->slot,
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OTX2_CPT_LF_DONE_WAIT, done_wait.u);
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}
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static void cptlf_do_set_done_num_wait(struct otx2_cptlf_info *lf, int num_wait)
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{
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union otx2_cptx_lf_done_wait done_wait;
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done_wait.u = otx2_cpt_read64(lf->lfs->reg_base, BLKADDR_CPT0, lf->slot,
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OTX2_CPT_LF_DONE_WAIT);
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done_wait.s.num_wait = num_wait;
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otx2_cpt_write64(lf->lfs->reg_base, BLKADDR_CPT0, lf->slot,
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OTX2_CPT_LF_DONE_WAIT, done_wait.u);
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}
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static void cptlf_set_done_time_wait(struct otx2_cptlfs_info *lfs,
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int time_wait)
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{
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int slot;
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for (slot = 0; slot < lfs->lfs_num; slot++)
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cptlf_do_set_done_time_wait(&lfs->lf[slot], time_wait);
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}
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static void cptlf_set_done_num_wait(struct otx2_cptlfs_info *lfs, int num_wait)
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{
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int slot;
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for (slot = 0; slot < lfs->lfs_num; slot++)
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cptlf_do_set_done_num_wait(&lfs->lf[slot], num_wait);
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}
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static int cptlf_set_pri(struct otx2_cptlf_info *lf, int pri)
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{
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struct otx2_cptlfs_info *lfs = lf->lfs;
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union otx2_cptx_af_lf_ctrl lf_ctrl;
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int ret;
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ret = otx2_cpt_read_af_reg(lfs->mbox, lfs->pdev,
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CPT_AF_LFX_CTL(lf->slot),
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&lf_ctrl.u, lfs->blkaddr);
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if (ret)
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return ret;
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lf_ctrl.s.pri = pri ? 1 : 0;
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ret = otx2_cpt_write_af_reg(lfs->mbox, lfs->pdev,
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CPT_AF_LFX_CTL(lf->slot),
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lf_ctrl.u, lfs->blkaddr);
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return ret;
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}
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static int cptlf_set_eng_grps_mask(struct otx2_cptlf_info *lf,
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int eng_grps_mask)
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{
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struct otx2_cptlfs_info *lfs = lf->lfs;
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union otx2_cptx_af_lf_ctrl lf_ctrl;
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int ret;
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ret = otx2_cpt_read_af_reg(lfs->mbox, lfs->pdev,
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CPT_AF_LFX_CTL(lf->slot),
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&lf_ctrl.u, lfs->blkaddr);
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if (ret)
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return ret;
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lf_ctrl.s.grp = eng_grps_mask;
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ret = otx2_cpt_write_af_reg(lfs->mbox, lfs->pdev,
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CPT_AF_LFX_CTL(lf->slot),
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lf_ctrl.u, lfs->blkaddr);
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return ret;
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}
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static int cptlf_set_grp_and_pri(struct otx2_cptlfs_info *lfs,
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int eng_grp_mask, int pri)
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{
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int slot, ret = 0;
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for (slot = 0; slot < lfs->lfs_num; slot++) {
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ret = cptlf_set_pri(&lfs->lf[slot], pri);
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if (ret)
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return ret;
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ret = cptlf_set_eng_grps_mask(&lfs->lf[slot], eng_grp_mask);
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if (ret)
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return ret;
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}
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return ret;
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}
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static void cptlf_hw_init(struct otx2_cptlfs_info *lfs)
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{
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/* Disable instruction queues */
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otx2_cptlf_disable_iqueues(lfs);
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/* Set instruction queues base addresses */
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otx2_cptlf_set_iqueues_base_addr(lfs);
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/* Set instruction queues sizes */
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otx2_cptlf_set_iqueues_size(lfs);
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/* Set done interrupts time wait */
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cptlf_set_done_time_wait(lfs, CPT_TIMER_HOLD);
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/* Set done interrupts num wait */
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cptlf_set_done_num_wait(lfs, CPT_COUNT_HOLD);
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/* Enable instruction queues */
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otx2_cptlf_enable_iqueues(lfs);
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}
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static void cptlf_hw_cleanup(struct otx2_cptlfs_info *lfs)
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{
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/* Disable instruction queues */
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otx2_cptlf_disable_iqueues(lfs);
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}
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static void cptlf_set_misc_intrs(struct otx2_cptlfs_info *lfs, u8 enable)
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{
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union otx2_cptx_lf_misc_int_ena_w1s irq_misc = { .u = 0x0 };
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u64 reg = enable ? OTX2_CPT_LF_MISC_INT_ENA_W1S :
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OTX2_CPT_LF_MISC_INT_ENA_W1C;
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int slot;
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irq_misc.s.fault = 0x1;
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irq_misc.s.hwerr = 0x1;
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irq_misc.s.irde = 0x1;
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irq_misc.s.nqerr = 0x1;
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irq_misc.s.nwrp = 0x1;
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for (slot = 0; slot < lfs->lfs_num; slot++)
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otx2_cpt_write64(lfs->reg_base, BLKADDR_CPT0, slot, reg,
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irq_misc.u);
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}
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static void cptlf_enable_intrs(struct otx2_cptlfs_info *lfs)
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{
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int slot;
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/* Enable done interrupts */
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for (slot = 0; slot < lfs->lfs_num; slot++)
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otx2_cpt_write64(lfs->reg_base, BLKADDR_CPT0, slot,
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OTX2_CPT_LF_DONE_INT_ENA_W1S, 0x1);
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/* Enable Misc interrupts */
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cptlf_set_misc_intrs(lfs, true);
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}
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static void cptlf_disable_intrs(struct otx2_cptlfs_info *lfs)
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{
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int slot;
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for (slot = 0; slot < lfs->lfs_num; slot++)
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otx2_cpt_write64(lfs->reg_base, BLKADDR_CPT0, slot,
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OTX2_CPT_LF_DONE_INT_ENA_W1C, 0x1);
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cptlf_set_misc_intrs(lfs, false);
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}
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static inline int cptlf_read_done_cnt(struct otx2_cptlf_info *lf)
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{
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union otx2_cptx_lf_done irq_cnt;
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irq_cnt.u = otx2_cpt_read64(lf->lfs->reg_base, BLKADDR_CPT0, lf->slot,
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OTX2_CPT_LF_DONE);
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return irq_cnt.s.done;
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}
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static irqreturn_t cptlf_misc_intr_handler(int __always_unused irq, void *arg)
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{
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union otx2_cptx_lf_misc_int irq_misc, irq_misc_ack;
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struct otx2_cptlf_info *lf = arg;
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struct device *dev;
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dev = &lf->lfs->pdev->dev;
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irq_misc.u = otx2_cpt_read64(lf->lfs->reg_base, BLKADDR_CPT0, lf->slot,
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OTX2_CPT_LF_MISC_INT);
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irq_misc_ack.u = 0x0;
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if (irq_misc.s.fault) {
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dev_err(dev, "Memory error detected while executing CPT_INST_S, LF %d.\n",
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lf->slot);
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irq_misc_ack.s.fault = 0x1;
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} else if (irq_misc.s.hwerr) {
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dev_err(dev, "HW error from an engine executing CPT_INST_S, LF %d.",
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lf->slot);
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irq_misc_ack.s.hwerr = 0x1;
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} else if (irq_misc.s.nwrp) {
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dev_err(dev, "SMMU fault while writing CPT_RES_S to CPT_INST_S[RES_ADDR], LF %d.\n",
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lf->slot);
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irq_misc_ack.s.nwrp = 0x1;
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} else if (irq_misc.s.irde) {
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dev_err(dev, "Memory error when accessing instruction memory queue CPT_LF_Q_BASE[ADDR].\n");
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irq_misc_ack.s.irde = 0x1;
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} else if (irq_misc.s.nqerr) {
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dev_err(dev, "Error enqueuing an instruction received at CPT_LF_NQ.\n");
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irq_misc_ack.s.nqerr = 0x1;
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} else {
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dev_err(dev, "Unhandled interrupt in CPT LF %d\n", lf->slot);
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return IRQ_NONE;
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}
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/* Acknowledge interrupts */
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otx2_cpt_write64(lf->lfs->reg_base, BLKADDR_CPT0, lf->slot,
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OTX2_CPT_LF_MISC_INT, irq_misc_ack.u);
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return IRQ_HANDLED;
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}
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static irqreturn_t cptlf_done_intr_handler(int irq, void *arg)
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{
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union otx2_cptx_lf_done_wait done_wait;
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struct otx2_cptlf_info *lf = arg;
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int irq_cnt;
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/* Read the number of completed requests */
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irq_cnt = cptlf_read_done_cnt(lf);
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if (irq_cnt) {
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done_wait.u = otx2_cpt_read64(lf->lfs->reg_base, BLKADDR_CPT0,
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lf->slot, OTX2_CPT_LF_DONE_WAIT);
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/* Acknowledge the number of completed requests */
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otx2_cpt_write64(lf->lfs->reg_base, BLKADDR_CPT0, lf->slot,
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OTX2_CPT_LF_DONE_ACK, irq_cnt);
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otx2_cpt_write64(lf->lfs->reg_base, BLKADDR_CPT0, lf->slot,
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OTX2_CPT_LF_DONE_WAIT, done_wait.u);
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if (unlikely(!lf->wqe)) {
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dev_err(&lf->lfs->pdev->dev, "No work for LF %d\n",
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lf->slot);
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return IRQ_NONE;
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}
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/* Schedule processing of completed requests */
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tasklet_hi_schedule(&lf->wqe->work);
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}
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return IRQ_HANDLED;
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}
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void otx2_cptlf_unregister_interrupts(struct otx2_cptlfs_info *lfs)
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{
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int i, offs, vector;
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for (i = 0; i < lfs->lfs_num; i++) {
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for (offs = 0; offs < OTX2_CPT_LF_MSIX_VECTORS; offs++) {
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if (!lfs->lf[i].is_irq_reg[offs])
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continue;
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vector = pci_irq_vector(lfs->pdev,
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lfs->lf[i].msix_offset + offs);
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free_irq(vector, &lfs->lf[i]);
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lfs->lf[i].is_irq_reg[offs] = false;
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}
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}
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cptlf_disable_intrs(lfs);
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}
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EXPORT_SYMBOL_NS_GPL(otx2_cptlf_unregister_interrupts,
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CRYPTO_DEV_OCTEONTX2_CPT);
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static int cptlf_do_register_interrrupts(struct otx2_cptlfs_info *lfs,
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int lf_num, int irq_offset,
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irq_handler_t handler)
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{
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int ret, vector;
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vector = pci_irq_vector(lfs->pdev, lfs->lf[lf_num].msix_offset +
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irq_offset);
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ret = request_irq(vector, handler, 0,
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lfs->lf[lf_num].irq_name[irq_offset],
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&lfs->lf[lf_num]);
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if (ret)
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return ret;
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lfs->lf[lf_num].is_irq_reg[irq_offset] = true;
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return ret;
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}
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int otx2_cptlf_register_interrupts(struct otx2_cptlfs_info *lfs)
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{
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int irq_offs, ret, i;
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for (i = 0; i < lfs->lfs_num; i++) {
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irq_offs = OTX2_CPT_LF_INT_VEC_E_MISC;
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snprintf(lfs->lf[i].irq_name[irq_offs], 32, "CPTLF Misc%d", i);
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ret = cptlf_do_register_interrrupts(lfs, i, irq_offs,
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cptlf_misc_intr_handler);
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if (ret)
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goto free_irq;
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irq_offs = OTX2_CPT_LF_INT_VEC_E_DONE;
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snprintf(lfs->lf[i].irq_name[irq_offs], 32, "OTX2_CPTLF Done%d",
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i);
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ret = cptlf_do_register_interrrupts(lfs, i, irq_offs,
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cptlf_done_intr_handler);
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if (ret)
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goto free_irq;
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}
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cptlf_enable_intrs(lfs);
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return 0;
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free_irq:
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otx2_cptlf_unregister_interrupts(lfs);
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return ret;
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}
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EXPORT_SYMBOL_NS_GPL(otx2_cptlf_register_interrupts, CRYPTO_DEV_OCTEONTX2_CPT);
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void otx2_cptlf_free_irqs_affinity(struct otx2_cptlfs_info *lfs)
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{
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int slot, offs;
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for (slot = 0; slot < lfs->lfs_num; slot++) {
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for (offs = 0; offs < OTX2_CPT_LF_MSIX_VECTORS; offs++)
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irq_set_affinity_hint(pci_irq_vector(lfs->pdev,
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lfs->lf[slot].msix_offset +
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offs), NULL);
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free_cpumask_var(lfs->lf[slot].affinity_mask);
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}
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}
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EXPORT_SYMBOL_NS_GPL(otx2_cptlf_free_irqs_affinity, CRYPTO_DEV_OCTEONTX2_CPT);
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int otx2_cptlf_set_irqs_affinity(struct otx2_cptlfs_info *lfs)
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{
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struct otx2_cptlf_info *lf = lfs->lf;
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int slot, offs, ret;
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for (slot = 0; slot < lfs->lfs_num; slot++) {
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if (!zalloc_cpumask_var(&lf[slot].affinity_mask, GFP_KERNEL)) {
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dev_err(&lfs->pdev->dev,
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"cpumask allocation failed for LF %d", slot);
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ret = -ENOMEM;
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goto free_affinity_mask;
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}
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cpumask_set_cpu(cpumask_local_spread(slot,
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dev_to_node(&lfs->pdev->dev)),
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lf[slot].affinity_mask);
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for (offs = 0; offs < OTX2_CPT_LF_MSIX_VECTORS; offs++) {
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ret = irq_set_affinity_hint(pci_irq_vector(lfs->pdev,
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lf[slot].msix_offset + offs),
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lf[slot].affinity_mask);
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if (ret)
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goto free_affinity_mask;
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}
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}
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return 0;
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free_affinity_mask:
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otx2_cptlf_free_irqs_affinity(lfs);
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return ret;
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}
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EXPORT_SYMBOL_NS_GPL(otx2_cptlf_set_irqs_affinity, CRYPTO_DEV_OCTEONTX2_CPT);
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int otx2_cptlf_init(struct otx2_cptlfs_info *lfs, u8 eng_grp_mask, int pri,
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int lfs_num)
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{
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int slot, ret;
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if (!lfs->pdev || !lfs->reg_base)
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return -EINVAL;
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lfs->lfs_num = lfs_num;
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for (slot = 0; slot < lfs->lfs_num; slot++) {
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lfs->lf[slot].lfs = lfs;
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lfs->lf[slot].slot = slot;
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if (lfs->lmt_base)
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lfs->lf[slot].lmtline = lfs->lmt_base +
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(slot * LMTLINE_SIZE);
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else
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lfs->lf[slot].lmtline = lfs->reg_base +
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OTX2_CPT_RVU_FUNC_ADDR_S(BLKADDR_LMT, slot,
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OTX2_CPT_LMT_LF_LMTLINEX(0));
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lfs->lf[slot].ioreg = lfs->reg_base +
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OTX2_CPT_RVU_FUNC_ADDR_S(BLKADDR_CPT0, slot,
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OTX2_CPT_LF_NQX(0));
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}
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/* Send request to attach LFs */
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ret = otx2_cpt_attach_rscrs_msg(lfs);
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if (ret)
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goto clear_lfs_num;
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ret = otx2_cpt_alloc_instruction_queues(lfs);
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if (ret) {
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dev_err(&lfs->pdev->dev,
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"Allocating instruction queues failed\n");
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goto detach_rsrcs;
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}
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cptlf_hw_init(lfs);
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/*
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* Allow each LF to execute requests destined to any of 8 engine
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* groups and set queue priority of each LF to high
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*/
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ret = cptlf_set_grp_and_pri(lfs, eng_grp_mask, pri);
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if (ret)
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goto free_iq;
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return 0;
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free_iq:
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otx2_cpt_free_instruction_queues(lfs);
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cptlf_hw_cleanup(lfs);
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detach_rsrcs:
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otx2_cpt_detach_rsrcs_msg(lfs);
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clear_lfs_num:
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lfs->lfs_num = 0;
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return ret;
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}
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EXPORT_SYMBOL_NS_GPL(otx2_cptlf_init, CRYPTO_DEV_OCTEONTX2_CPT);
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void otx2_cptlf_shutdown(struct otx2_cptlfs_info *lfs)
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{
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lfs->lfs_num = 0;
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/* Cleanup LFs hardware side */
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cptlf_hw_cleanup(lfs);
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/* Send request to detach LFs */
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otx2_cpt_detach_rsrcs_msg(lfs);
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}
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EXPORT_SYMBOL_NS_GPL(otx2_cptlf_shutdown, CRYPTO_DEV_OCTEONTX2_CPT);
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MODULE_AUTHOR("Marvell");
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MODULE_DESCRIPTION("Marvell RVU CPT Common module");
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MODULE_LICENSE("GPL");
|