161 lines
4.0 KiB
C
161 lines
4.0 KiB
C
/* SPDX-License-Identifier: GPL-2.0-only
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* Copyright (C) 2020 Marvell.
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*/
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#ifndef __OTX2_CPT_COMMON_H
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#define __OTX2_CPT_COMMON_H
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#include <linux/pci.h>
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#include <linux/types.h>
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#include <linux/module.h>
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#include <linux/delay.h>
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#include <linux/crypto.h>
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#include <net/devlink.h>
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#include "otx2_cpt_hw_types.h"
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#include "rvu.h"
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#include "mbox.h"
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#define OTX2_CPT_MAX_VFS_NUM 128
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#define OTX2_CPT_RVU_FUNC_ADDR_S(blk, slot, offs) \
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(((blk) << 20) | ((slot) << 12) | (offs))
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#define OTX2_CPT_RVU_PFFUNC(pf, func) \
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((((pf) & RVU_PFVF_PF_MASK) << RVU_PFVF_PF_SHIFT) | \
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(((func) & RVU_PFVF_FUNC_MASK) << RVU_PFVF_FUNC_SHIFT))
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#define OTX2_CPT_INVALID_CRYPTO_ENG_GRP 0xFF
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#define OTX2_CPT_NAME_LENGTH 64
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#define OTX2_CPT_DMA_MINALIGN 128
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/* HW capability flags */
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#define CN10K_MBOX 0
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#define CN10K_LMTST 1
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#define BAD_OTX2_CPT_ENG_TYPE OTX2_CPT_MAX_ENG_TYPES
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enum otx2_cpt_eng_type {
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OTX2_CPT_AE_TYPES = 1,
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OTX2_CPT_SE_TYPES = 2,
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OTX2_CPT_IE_TYPES = 3,
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OTX2_CPT_MAX_ENG_TYPES,
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};
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/* Take mbox id from end of CPT mbox range in AF (range 0xA00 - 0xBFF) */
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#define MBOX_MSG_GET_ENG_GRP_NUM 0xBFF
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#define MBOX_MSG_GET_CAPS 0xBFD
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#define MBOX_MSG_GET_KVF_LIMITS 0xBFC
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/*
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* Message request and response to get engine group number
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* which has attached a given type of engines (SE, AE, IE)
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* This messages are only used between CPT PF <=> CPT VF
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*/
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struct otx2_cpt_egrp_num_msg {
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struct mbox_msghdr hdr;
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u8 eng_type;
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};
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struct otx2_cpt_egrp_num_rsp {
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struct mbox_msghdr hdr;
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u8 eng_type;
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u8 eng_grp_num;
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};
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/*
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* Message request and response to get kernel crypto limits
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* This messages are only used between CPT PF <-> CPT VF
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*/
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struct otx2_cpt_kvf_limits_msg {
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struct mbox_msghdr hdr;
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};
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struct otx2_cpt_kvf_limits_rsp {
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struct mbox_msghdr hdr;
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u8 kvf_limits;
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};
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/* CPT HW capabilities */
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union otx2_cpt_eng_caps {
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u64 u;
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struct {
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u64 reserved_0_4:5;
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u64 mul:1;
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u64 sha1_sha2:1;
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u64 chacha20:1;
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u64 zuc_snow3g:1;
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u64 sha3:1;
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u64 aes:1;
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u64 kasumi:1;
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u64 des:1;
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u64 crc:1;
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u64 reserved_14_63:50;
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};
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};
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/*
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* Message request and response to get HW capabilities for each
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* engine type (SE, IE, AE).
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* This messages are only used between CPT PF <=> CPT VF
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*/
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struct otx2_cpt_caps_msg {
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struct mbox_msghdr hdr;
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};
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struct otx2_cpt_caps_rsp {
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struct mbox_msghdr hdr;
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u16 cpt_pf_drv_version;
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u8 cpt_revision;
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union otx2_cpt_eng_caps eng_caps[OTX2_CPT_MAX_ENG_TYPES];
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};
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static inline void otx2_cpt_write64(void __iomem *reg_base, u64 blk, u64 slot,
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u64 offs, u64 val)
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{
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writeq_relaxed(val, reg_base +
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OTX2_CPT_RVU_FUNC_ADDR_S(blk, slot, offs));
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}
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static inline u64 otx2_cpt_read64(void __iomem *reg_base, u64 blk, u64 slot,
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u64 offs)
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{
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return readq_relaxed(reg_base +
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OTX2_CPT_RVU_FUNC_ADDR_S(blk, slot, offs));
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}
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static inline bool is_dev_otx2(struct pci_dev *pdev)
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{
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if (pdev->device == OTX2_CPT_PCI_PF_DEVICE_ID ||
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pdev->device == OTX2_CPT_PCI_VF_DEVICE_ID)
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return true;
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return false;
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}
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static inline void otx2_cpt_set_hw_caps(struct pci_dev *pdev,
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unsigned long *cap_flag)
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{
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if (!is_dev_otx2(pdev)) {
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__set_bit(CN10K_MBOX, cap_flag);
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__set_bit(CN10K_LMTST, cap_flag);
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}
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}
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int otx2_cpt_send_ready_msg(struct otx2_mbox *mbox, struct pci_dev *pdev);
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int otx2_cpt_send_mbox_msg(struct otx2_mbox *mbox, struct pci_dev *pdev);
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int otx2_cpt_send_af_reg_requests(struct otx2_mbox *mbox,
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struct pci_dev *pdev);
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int otx2_cpt_add_write_af_reg(struct otx2_mbox *mbox, struct pci_dev *pdev,
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u64 reg, u64 val, int blkaddr);
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int otx2_cpt_read_af_reg(struct otx2_mbox *mbox, struct pci_dev *pdev,
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u64 reg, u64 *val, int blkaddr);
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int otx2_cpt_write_af_reg(struct otx2_mbox *mbox, struct pci_dev *pdev,
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u64 reg, u64 val, int blkaddr);
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struct otx2_cptlfs_info;
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int otx2_cpt_attach_rscrs_msg(struct otx2_cptlfs_info *lfs);
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int otx2_cpt_detach_rsrcs_msg(struct otx2_cptlfs_info *lfs);
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int otx2_cpt_msix_offset_msg(struct otx2_cptlfs_info *lfs);
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int otx2_cpt_sync_mbox_msg(struct otx2_mbox *mbox);
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#endif /* __OTX2_CPT_COMMON_H */
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