710 lines
18 KiB
C
710 lines
18 KiB
C
// SPDX-License-Identifier: GPL-2.0
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/*
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* unaligned.c: Unaligned load/store trap handling with special
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* cases for the kernel to do them more quickly.
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*
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* Copyright (C) 1996,2008 David S. Miller (davem@davemloft.net)
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* Copyright (C) 1996,1997 Jakub Jelinek (jj@sunsite.mff.cuni.cz)
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*/
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#include <linux/jiffies.h>
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#include <linux/kernel.h>
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#include <linux/sched.h>
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#include <linux/mm.h>
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#include <linux/extable.h>
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#include <asm/asi.h>
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#include <asm/ptrace.h>
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#include <asm/pstate.h>
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#include <asm/processor.h>
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#include <linux/uaccess.h>
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#include <linux/smp.h>
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#include <linux/bitops.h>
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#include <linux/perf_event.h>
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#include <linux/ratelimit.h>
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#include <linux/context_tracking.h>
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#include <asm/fpumacro.h>
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#include <asm/cacheflush.h>
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#include <asm/setup.h>
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#include "entry.h"
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#include "kernel.h"
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enum direction {
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load, /* ld, ldd, ldh, ldsh */
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store, /* st, std, sth, stsh */
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both, /* Swap, ldstub, cas, ... */
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fpld,
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fpst,
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invalid,
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};
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static inline enum direction decode_direction(unsigned int insn)
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{
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unsigned long tmp = (insn >> 21) & 1;
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if (!tmp)
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return load;
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else {
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switch ((insn>>19)&0xf) {
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case 15: /* swap* */
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return both;
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default:
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return store;
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}
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}
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}
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/* 16 = double-word, 8 = extra-word, 4 = word, 2 = half-word */
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static inline int decode_access_size(struct pt_regs *regs, unsigned int insn)
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{
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unsigned int tmp;
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tmp = ((insn >> 19) & 0xf);
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if (tmp == 11 || tmp == 14) /* ldx/stx */
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return 8;
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tmp &= 3;
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if (!tmp)
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return 4;
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else if (tmp == 3)
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return 16; /* ldd/std - Although it is actually 8 */
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else if (tmp == 2)
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return 2;
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else {
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printk("Impossible unaligned trap. insn=%08x\n", insn);
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die_if_kernel("Byte sized unaligned access?!?!", regs);
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/* GCC should never warn that control reaches the end
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* of this function without returning a value because
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* die_if_kernel() is marked with attribute 'noreturn'.
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* Alas, some versions do...
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*/
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return 0;
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}
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}
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static inline int decode_asi(unsigned int insn, struct pt_regs *regs)
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{
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if (insn & 0x800000) {
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if (insn & 0x2000)
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return (unsigned char)(regs->tstate >> 24); /* %asi */
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else
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return (unsigned char)(insn >> 5); /* imm_asi */
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} else
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return ASI_P;
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}
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/* 0x400000 = signed, 0 = unsigned */
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static inline int decode_signedness(unsigned int insn)
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{
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return (insn & 0x400000);
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}
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static inline void maybe_flush_windows(unsigned int rs1, unsigned int rs2,
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unsigned int rd, int from_kernel)
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{
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if (rs2 >= 16 || rs1 >= 16 || rd >= 16) {
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if (from_kernel != 0)
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__asm__ __volatile__("flushw");
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else
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flushw_user();
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}
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}
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static inline long sign_extend_imm13(long imm)
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{
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return imm << 51 >> 51;
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}
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static unsigned long fetch_reg(unsigned int reg, struct pt_regs *regs)
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{
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unsigned long value, fp;
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if (reg < 16)
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return (!reg ? 0 : regs->u_regs[reg]);
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fp = regs->u_regs[UREG_FP];
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if (regs->tstate & TSTATE_PRIV) {
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struct reg_window *win;
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win = (struct reg_window *)(fp + STACK_BIAS);
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value = win->locals[reg - 16];
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} else if (!test_thread_64bit_stack(fp)) {
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struct reg_window32 __user *win32;
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win32 = (struct reg_window32 __user *)((unsigned long)((u32)fp));
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get_user(value, &win32->locals[reg - 16]);
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} else {
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struct reg_window __user *win;
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win = (struct reg_window __user *)(fp + STACK_BIAS);
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get_user(value, &win->locals[reg - 16]);
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}
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return value;
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}
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static unsigned long *fetch_reg_addr(unsigned int reg, struct pt_regs *regs)
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{
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unsigned long fp;
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if (reg < 16)
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return ®s->u_regs[reg];
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fp = regs->u_regs[UREG_FP];
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if (regs->tstate & TSTATE_PRIV) {
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struct reg_window *win;
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win = (struct reg_window *)(fp + STACK_BIAS);
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return &win->locals[reg - 16];
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} else if (!test_thread_64bit_stack(fp)) {
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struct reg_window32 *win32;
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win32 = (struct reg_window32 *)((unsigned long)((u32)fp));
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return (unsigned long *)&win32->locals[reg - 16];
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} else {
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struct reg_window *win;
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win = (struct reg_window *)(fp + STACK_BIAS);
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return &win->locals[reg - 16];
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}
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}
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unsigned long compute_effective_address(struct pt_regs *regs,
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unsigned int insn, unsigned int rd)
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{
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int from_kernel = (regs->tstate & TSTATE_PRIV) != 0;
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unsigned int rs1 = (insn >> 14) & 0x1f;
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unsigned int rs2 = insn & 0x1f;
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unsigned long addr;
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if (insn & 0x2000) {
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maybe_flush_windows(rs1, 0, rd, from_kernel);
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addr = (fetch_reg(rs1, regs) + sign_extend_imm13(insn));
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} else {
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maybe_flush_windows(rs1, rs2, rd, from_kernel);
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addr = (fetch_reg(rs1, regs) + fetch_reg(rs2, regs));
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}
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if (!from_kernel && test_thread_flag(TIF_32BIT))
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addr &= 0xffffffff;
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return addr;
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}
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/* This is just to make gcc think die_if_kernel does return... */
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static void __used unaligned_panic(char *str, struct pt_regs *regs)
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{
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die_if_kernel(str, regs);
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}
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extern int do_int_load(unsigned long *dest_reg, int size,
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unsigned long *saddr, int is_signed, int asi);
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extern int __do_int_store(unsigned long *dst_addr, int size,
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unsigned long src_val, int asi);
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static inline int do_int_store(int reg_num, int size, unsigned long *dst_addr,
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struct pt_regs *regs, int asi, int orig_asi)
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{
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unsigned long zero = 0;
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unsigned long *src_val_p = &zero;
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unsigned long src_val;
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if (size == 16) {
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size = 8;
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zero = (((long)(reg_num ?
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(unsigned int)fetch_reg(reg_num, regs) : 0)) << 32) |
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(unsigned int)fetch_reg(reg_num + 1, regs);
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} else if (reg_num) {
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src_val_p = fetch_reg_addr(reg_num, regs);
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}
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src_val = *src_val_p;
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if (unlikely(asi != orig_asi)) {
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switch (size) {
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case 2:
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src_val = swab16(src_val);
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break;
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case 4:
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src_val = swab32(src_val);
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break;
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case 8:
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src_val = swab64(src_val);
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break;
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case 16:
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default:
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BUG();
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break;
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}
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}
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return __do_int_store(dst_addr, size, src_val, asi);
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}
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static inline void advance(struct pt_regs *regs)
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{
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regs->tpc = regs->tnpc;
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regs->tnpc += 4;
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if (test_thread_flag(TIF_32BIT)) {
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regs->tpc &= 0xffffffff;
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regs->tnpc &= 0xffffffff;
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}
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}
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static inline int floating_point_load_or_store_p(unsigned int insn)
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{
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return (insn >> 24) & 1;
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}
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static inline int ok_for_kernel(unsigned int insn)
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{
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return !floating_point_load_or_store_p(insn);
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}
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static void kernel_mna_trap_fault(int fixup_tstate_asi)
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{
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struct pt_regs *regs = current_thread_info()->kern_una_regs;
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unsigned int insn = current_thread_info()->kern_una_insn;
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const struct exception_table_entry *entry;
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entry = search_exception_tables(regs->tpc);
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if (!entry) {
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unsigned long address;
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address = compute_effective_address(regs, insn,
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((insn >> 25) & 0x1f));
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if (address < PAGE_SIZE) {
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printk(KERN_ALERT "Unable to handle kernel NULL "
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"pointer dereference in mna handler");
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} else
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printk(KERN_ALERT "Unable to handle kernel paging "
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"request in mna handler");
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printk(KERN_ALERT " at virtual address %016lx\n",address);
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printk(KERN_ALERT "current->{active_,}mm->context = %016lx\n",
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(current->mm ? CTX_HWBITS(current->mm->context) :
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CTX_HWBITS(current->active_mm->context)));
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printk(KERN_ALERT "current->{active_,}mm->pgd = %016lx\n",
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(current->mm ? (unsigned long) current->mm->pgd :
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(unsigned long) current->active_mm->pgd));
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die_if_kernel("Oops", regs);
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/* Not reached */
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}
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regs->tpc = entry->fixup;
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regs->tnpc = regs->tpc + 4;
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if (fixup_tstate_asi) {
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regs->tstate &= ~TSTATE_ASI;
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regs->tstate |= (ASI_AIUS << 24UL);
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}
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}
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static void log_unaligned(struct pt_regs *regs)
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{
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static DEFINE_RATELIMIT_STATE(ratelimit, 5 * HZ, 5);
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if (__ratelimit(&ratelimit)) {
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printk("Kernel unaligned access at TPC[%lx] %pS\n",
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regs->tpc, (void *) regs->tpc);
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}
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}
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asmlinkage void kernel_unaligned_trap(struct pt_regs *regs, unsigned int insn)
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{
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enum direction dir = decode_direction(insn);
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int size = decode_access_size(regs, insn);
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int orig_asi, asi;
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current_thread_info()->kern_una_regs = regs;
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current_thread_info()->kern_una_insn = insn;
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orig_asi = asi = decode_asi(insn, regs);
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/* If this is a {get,put}_user() on an unaligned userspace pointer,
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* just signal a fault and do not log the event.
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*/
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if (asi == ASI_AIUS) {
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kernel_mna_trap_fault(0);
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return;
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}
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log_unaligned(regs);
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if (!ok_for_kernel(insn) || dir == both) {
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printk("Unsupported unaligned load/store trap for kernel "
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"at <%016lx>.\n", regs->tpc);
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unaligned_panic("Kernel does fpu/atomic "
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"unaligned load/store.", regs);
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kernel_mna_trap_fault(0);
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} else {
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unsigned long addr, *reg_addr;
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int err;
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addr = compute_effective_address(regs, insn,
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((insn >> 25) & 0x1f));
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perf_sw_event(PERF_COUNT_SW_ALIGNMENT_FAULTS, 1, regs, addr);
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switch (asi) {
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case ASI_NL:
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case ASI_AIUPL:
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case ASI_AIUSL:
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case ASI_PL:
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case ASI_SL:
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case ASI_PNFL:
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case ASI_SNFL:
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asi &= ~0x08;
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break;
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}
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switch (dir) {
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case load:
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reg_addr = fetch_reg_addr(((insn>>25)&0x1f), regs);
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err = do_int_load(reg_addr, size,
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(unsigned long *) addr,
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decode_signedness(insn), asi);
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if (likely(!err) && unlikely(asi != orig_asi)) {
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unsigned long val_in = *reg_addr;
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switch (size) {
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case 2:
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val_in = swab16(val_in);
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break;
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case 4:
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val_in = swab32(val_in);
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break;
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case 8:
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val_in = swab64(val_in);
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break;
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case 16:
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default:
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BUG();
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break;
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}
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*reg_addr = val_in;
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}
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break;
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case store:
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err = do_int_store(((insn>>25)&0x1f), size,
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(unsigned long *) addr, regs,
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asi, orig_asi);
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break;
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default:
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panic("Impossible kernel unaligned trap.");
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/* Not reached... */
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}
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if (unlikely(err))
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kernel_mna_trap_fault(1);
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else
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advance(regs);
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}
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}
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int handle_popc(u32 insn, struct pt_regs *regs)
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{
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int from_kernel = (regs->tstate & TSTATE_PRIV) != 0;
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int ret, rd = ((insn >> 25) & 0x1f);
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u64 value;
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perf_sw_event(PERF_COUNT_SW_EMULATION_FAULTS, 1, regs, 0);
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if (insn & 0x2000) {
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maybe_flush_windows(0, 0, rd, from_kernel);
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value = sign_extend_imm13(insn);
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} else {
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maybe_flush_windows(0, insn & 0x1f, rd, from_kernel);
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value = fetch_reg(insn & 0x1f, regs);
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}
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ret = hweight64(value);
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if (rd < 16) {
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if (rd)
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regs->u_regs[rd] = ret;
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} else {
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unsigned long fp = regs->u_regs[UREG_FP];
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if (!test_thread_64bit_stack(fp)) {
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struct reg_window32 __user *win32;
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win32 = (struct reg_window32 __user *)((unsigned long)((u32)fp));
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put_user(ret, &win32->locals[rd - 16]);
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} else {
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struct reg_window __user *win;
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win = (struct reg_window __user *)(fp + STACK_BIAS);
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put_user(ret, &win->locals[rd - 16]);
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}
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}
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advance(regs);
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return 1;
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}
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extern void do_fpother(struct pt_regs *regs);
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extern void do_privact(struct pt_regs *regs);
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extern void sun4v_data_access_exception(struct pt_regs *regs,
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unsigned long addr,
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unsigned long type_ctx);
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int handle_ldf_stq(u32 insn, struct pt_regs *regs)
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{
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unsigned long addr = compute_effective_address(regs, insn, 0);
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int freg;
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struct fpustate *f = FPUSTATE;
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int asi = decode_asi(insn, regs);
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int flag;
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perf_sw_event(PERF_COUNT_SW_EMULATION_FAULTS, 1, regs, 0);
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save_and_clear_fpu();
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current_thread_info()->xfsr[0] &= ~0x1c000;
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if (insn & 0x200000) {
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/* STQ */
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u64 first = 0, second = 0;
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freg = ((insn >> 25) & 0x1e) | ((insn >> 20) & 0x20);
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flag = (freg < 32) ? FPRS_DL : FPRS_DU;
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if (freg & 3) {
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current_thread_info()->xfsr[0] |= (6 << 14) /* invalid_fp_register */;
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do_fpother(regs);
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return 0;
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}
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if (current_thread_info()->fpsaved[0] & flag) {
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first = *(u64 *)&f->regs[freg];
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second = *(u64 *)&f->regs[freg+2];
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}
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if (asi < 0x80) {
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do_privact(regs);
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return 1;
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}
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switch (asi) {
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case ASI_P:
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case ASI_S: break;
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case ASI_PL:
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case ASI_SL:
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{
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/* Need to convert endians */
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u64 tmp = __swab64p(&first);
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first = __swab64p(&second);
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second = tmp;
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break;
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}
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default:
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if (tlb_type == hypervisor)
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sun4v_data_access_exception(regs, addr, 0);
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else
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spitfire_data_access_exception(regs, 0, addr);
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return 1;
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}
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if (put_user (first >> 32, (u32 __user *)addr) ||
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__put_user ((u32)first, (u32 __user *)(addr + 4)) ||
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__put_user (second >> 32, (u32 __user *)(addr + 8)) ||
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__put_user ((u32)second, (u32 __user *)(addr + 12))) {
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if (tlb_type == hypervisor)
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sun4v_data_access_exception(regs, addr, 0);
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else
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spitfire_data_access_exception(regs, 0, addr);
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return 1;
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}
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} else {
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/* LDF, LDDF, LDQF */
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u32 data[4] __attribute__ ((aligned(8)));
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int size, i;
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int err;
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if (asi < 0x80) {
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do_privact(regs);
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return 1;
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} else if (asi > ASI_SNFL) {
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if (tlb_type == hypervisor)
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sun4v_data_access_exception(regs, addr, 0);
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else
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spitfire_data_access_exception(regs, 0, addr);
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return 1;
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}
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switch (insn & 0x180000) {
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case 0x000000: size = 1; break;
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case 0x100000: size = 4; break;
|
|
default: size = 2; break;
|
|
}
|
|
if (size == 1)
|
|
freg = (insn >> 25) & 0x1f;
|
|
else
|
|
freg = ((insn >> 25) & 0x1e) | ((insn >> 20) & 0x20);
|
|
flag = (freg < 32) ? FPRS_DL : FPRS_DU;
|
|
|
|
for (i = 0; i < size; i++)
|
|
data[i] = 0;
|
|
|
|
err = get_user (data[0], (u32 __user *) addr);
|
|
if (!err) {
|
|
for (i = 1; i < size; i++)
|
|
err |= __get_user (data[i], (u32 __user *)(addr + 4*i));
|
|
}
|
|
if (err && !(asi & 0x2 /* NF */)) {
|
|
if (tlb_type == hypervisor)
|
|
sun4v_data_access_exception(regs, addr, 0);
|
|
else
|
|
spitfire_data_access_exception(regs, 0, addr);
|
|
return 1;
|
|
}
|
|
if (asi & 0x8) /* Little */ {
|
|
u64 tmp;
|
|
|
|
switch (size) {
|
|
case 1: data[0] = le32_to_cpup(data + 0); break;
|
|
default:*(u64 *)(data + 0) = le64_to_cpup((u64 *)(data + 0));
|
|
break;
|
|
case 4: tmp = le64_to_cpup((u64 *)(data + 0));
|
|
*(u64 *)(data + 0) = le64_to_cpup((u64 *)(data + 2));
|
|
*(u64 *)(data + 2) = tmp;
|
|
break;
|
|
}
|
|
}
|
|
if (!(current_thread_info()->fpsaved[0] & FPRS_FEF)) {
|
|
current_thread_info()->fpsaved[0] = FPRS_FEF;
|
|
current_thread_info()->gsr[0] = 0;
|
|
}
|
|
if (!(current_thread_info()->fpsaved[0] & flag)) {
|
|
if (freg < 32)
|
|
memset(f->regs, 0, 32*sizeof(u32));
|
|
else
|
|
memset(f->regs+32, 0, 32*sizeof(u32));
|
|
}
|
|
memcpy(f->regs + freg, data, size * 4);
|
|
current_thread_info()->fpsaved[0] |= flag;
|
|
}
|
|
advance(regs);
|
|
return 1;
|
|
}
|
|
|
|
void handle_ld_nf(u32 insn, struct pt_regs *regs)
|
|
{
|
|
int rd = ((insn >> 25) & 0x1f);
|
|
int from_kernel = (regs->tstate & TSTATE_PRIV) != 0;
|
|
unsigned long *reg;
|
|
|
|
perf_sw_event(PERF_COUNT_SW_EMULATION_FAULTS, 1, regs, 0);
|
|
|
|
maybe_flush_windows(0, 0, rd, from_kernel);
|
|
reg = fetch_reg_addr(rd, regs);
|
|
if (from_kernel || rd < 16) {
|
|
reg[0] = 0;
|
|
if ((insn & 0x780000) == 0x180000)
|
|
reg[1] = 0;
|
|
} else if (!test_thread_64bit_stack(regs->u_regs[UREG_FP])) {
|
|
put_user(0, (int __user *) reg);
|
|
if ((insn & 0x780000) == 0x180000)
|
|
put_user(0, ((int __user *) reg) + 1);
|
|
} else {
|
|
put_user(0, (unsigned long __user *) reg);
|
|
if ((insn & 0x780000) == 0x180000)
|
|
put_user(0, (unsigned long __user *) reg + 1);
|
|
}
|
|
advance(regs);
|
|
}
|
|
|
|
void handle_lddfmna(struct pt_regs *regs, unsigned long sfar, unsigned long sfsr)
|
|
{
|
|
enum ctx_state prev_state = exception_enter();
|
|
unsigned long pc = regs->tpc;
|
|
unsigned long tstate = regs->tstate;
|
|
u32 insn;
|
|
u64 value;
|
|
u8 freg;
|
|
int flag;
|
|
struct fpustate *f = FPUSTATE;
|
|
|
|
if (tstate & TSTATE_PRIV)
|
|
die_if_kernel("lddfmna from kernel", regs);
|
|
perf_sw_event(PERF_COUNT_SW_ALIGNMENT_FAULTS, 1, regs, sfar);
|
|
if (test_thread_flag(TIF_32BIT))
|
|
pc = (u32)pc;
|
|
if (get_user(insn, (u32 __user *) pc) != -EFAULT) {
|
|
int asi = decode_asi(insn, regs);
|
|
u32 first, second;
|
|
int err;
|
|
|
|
if ((asi > ASI_SNFL) ||
|
|
(asi < ASI_P))
|
|
goto daex;
|
|
first = second = 0;
|
|
err = get_user(first, (u32 __user *)sfar);
|
|
if (!err)
|
|
err = get_user(second, (u32 __user *)(sfar + 4));
|
|
if (err) {
|
|
if (!(asi & 0x2))
|
|
goto daex;
|
|
first = second = 0;
|
|
}
|
|
save_and_clear_fpu();
|
|
freg = ((insn >> 25) & 0x1e) | ((insn >> 20) & 0x20);
|
|
value = (((u64)first) << 32) | second;
|
|
if (asi & 0x8) /* Little */
|
|
value = __swab64p(&value);
|
|
flag = (freg < 32) ? FPRS_DL : FPRS_DU;
|
|
if (!(current_thread_info()->fpsaved[0] & FPRS_FEF)) {
|
|
current_thread_info()->fpsaved[0] = FPRS_FEF;
|
|
current_thread_info()->gsr[0] = 0;
|
|
}
|
|
if (!(current_thread_info()->fpsaved[0] & flag)) {
|
|
if (freg < 32)
|
|
memset(f->regs, 0, 32*sizeof(u32));
|
|
else
|
|
memset(f->regs+32, 0, 32*sizeof(u32));
|
|
}
|
|
*(u64 *)(f->regs + freg) = value;
|
|
current_thread_info()->fpsaved[0] |= flag;
|
|
} else {
|
|
daex:
|
|
if (tlb_type == hypervisor)
|
|
sun4v_data_access_exception(regs, sfar, sfsr);
|
|
else
|
|
spitfire_data_access_exception(regs, sfsr, sfar);
|
|
goto out;
|
|
}
|
|
advance(regs);
|
|
out:
|
|
exception_exit(prev_state);
|
|
}
|
|
|
|
void handle_stdfmna(struct pt_regs *regs, unsigned long sfar, unsigned long sfsr)
|
|
{
|
|
enum ctx_state prev_state = exception_enter();
|
|
unsigned long pc = regs->tpc;
|
|
unsigned long tstate = regs->tstate;
|
|
u32 insn;
|
|
u64 value;
|
|
u8 freg;
|
|
int flag;
|
|
struct fpustate *f = FPUSTATE;
|
|
|
|
if (tstate & TSTATE_PRIV)
|
|
die_if_kernel("stdfmna from kernel", regs);
|
|
perf_sw_event(PERF_COUNT_SW_ALIGNMENT_FAULTS, 1, regs, sfar);
|
|
if (test_thread_flag(TIF_32BIT))
|
|
pc = (u32)pc;
|
|
if (get_user(insn, (u32 __user *) pc) != -EFAULT) {
|
|
int asi = decode_asi(insn, regs);
|
|
freg = ((insn >> 25) & 0x1e) | ((insn >> 20) & 0x20);
|
|
value = 0;
|
|
flag = (freg < 32) ? FPRS_DL : FPRS_DU;
|
|
if ((asi > ASI_SNFL) ||
|
|
(asi < ASI_P))
|
|
goto daex;
|
|
save_and_clear_fpu();
|
|
if (current_thread_info()->fpsaved[0] & flag)
|
|
value = *(u64 *)&f->regs[freg];
|
|
switch (asi) {
|
|
case ASI_P:
|
|
case ASI_S: break;
|
|
case ASI_PL:
|
|
case ASI_SL:
|
|
value = __swab64p(&value); break;
|
|
default: goto daex;
|
|
}
|
|
if (put_user (value >> 32, (u32 __user *) sfar) ||
|
|
__put_user ((u32)value, (u32 __user *)(sfar + 4)))
|
|
goto daex;
|
|
} else {
|
|
daex:
|
|
if (tlb_type == hypervisor)
|
|
sun4v_data_access_exception(regs, sfar, sfsr);
|
|
else
|
|
spitfire_data_access_exception(regs, sfsr, sfar);
|
|
goto out;
|
|
}
|
|
advance(regs);
|
|
out:
|
|
exception_exit(prev_state);
|
|
}
|