109 lines
2.8 KiB
C
109 lines
2.8 KiB
C
// SPDX-License-Identifier: GPL-2.0
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/*
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* arch/sh/kernel/cpu/sh3/probe.c
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*
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* CPU Subtype Probing for SH-3.
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*
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* Copyright (C) 1999, 2000 Niibe Yutaka
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* Copyright (C) 2002 Paul Mundt
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*/
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#include <linux/init.h>
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#include <asm/processor.h>
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#include <asm/cache.h>
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#include <asm/io.h>
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void cpu_probe(void)
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{
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unsigned long addr0, addr1, data0, data1, data2, data3;
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jump_to_uncached();
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/*
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* Check if the entry shadows or not.
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* When shadowed, it's 128-entry system.
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* Otherwise, it's 256-entry system.
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*/
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addr0 = CACHE_OC_ADDRESS_ARRAY + (3 << 12);
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addr1 = CACHE_OC_ADDRESS_ARRAY + (1 << 12);
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/* First, write back & invalidate */
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data0 = __raw_readl(addr0);
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__raw_writel(data0&~(SH_CACHE_VALID|SH_CACHE_UPDATED), addr0);
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data1 = __raw_readl(addr1);
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__raw_writel(data1&~(SH_CACHE_VALID|SH_CACHE_UPDATED), addr1);
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/* Next, check if there's shadow or not */
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data0 = __raw_readl(addr0);
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data0 ^= SH_CACHE_VALID;
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__raw_writel(data0, addr0);
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data1 = __raw_readl(addr1);
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data2 = data1 ^ SH_CACHE_VALID;
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__raw_writel(data2, addr1);
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data3 = __raw_readl(addr0);
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/* Lastly, invaliate them. */
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__raw_writel(data0&~SH_CACHE_VALID, addr0);
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__raw_writel(data2&~SH_CACHE_VALID, addr1);
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back_to_cached();
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boot_cpu_data.dcache.ways = 4;
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boot_cpu_data.dcache.entry_shift = 4;
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boot_cpu_data.dcache.linesz = L1_CACHE_BYTES;
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boot_cpu_data.dcache.flags = 0;
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/*
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* 7709A/7729 has 16K cache (256-entry), while 7702 has only
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* 2K(direct) 7702 is not supported (yet)
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*/
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if (data0 == data1 && data2 == data3) { /* Shadow */
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boot_cpu_data.dcache.way_incr = (1 << 11);
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boot_cpu_data.dcache.entry_mask = 0x7f0;
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boot_cpu_data.dcache.sets = 128;
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boot_cpu_data.type = CPU_SH7708;
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boot_cpu_data.flags |= CPU_HAS_MMU_PAGE_ASSOC;
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} else { /* 7709A or 7729 */
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boot_cpu_data.dcache.way_incr = (1 << 12);
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boot_cpu_data.dcache.entry_mask = 0xff0;
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boot_cpu_data.dcache.sets = 256;
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boot_cpu_data.type = CPU_SH7729;
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#if defined(CONFIG_CPU_SUBTYPE_SH7706)
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boot_cpu_data.type = CPU_SH7706;
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#endif
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#if defined(CONFIG_CPU_SUBTYPE_SH7710)
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boot_cpu_data.type = CPU_SH7710;
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#endif
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#if defined(CONFIG_CPU_SUBTYPE_SH7712)
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boot_cpu_data.type = CPU_SH7712;
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#endif
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#if defined(CONFIG_CPU_SUBTYPE_SH7720)
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boot_cpu_data.type = CPU_SH7720;
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#endif
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#if defined(CONFIG_CPU_SUBTYPE_SH7721)
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boot_cpu_data.type = CPU_SH7721;
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#endif
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#if defined(CONFIG_CPU_SUBTYPE_SH7705)
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boot_cpu_data.type = CPU_SH7705;
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#if defined(CONFIG_SH7705_CACHE_32KB)
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boot_cpu_data.dcache.way_incr = (1 << 13);
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boot_cpu_data.dcache.entry_mask = 0x1ff0;
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boot_cpu_data.dcache.sets = 512;
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__raw_writel(CCR_CACHE_32KB, CCR3_REG);
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#else
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__raw_writel(CCR_CACHE_16KB, CCR3_REG);
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#endif
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#endif
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}
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/*
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* SH-3 doesn't have separate caches
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*/
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boot_cpu_data.dcache.flags |= SH_CACHE_COMBINED;
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boot_cpu_data.icache = boot_cpu_data.dcache;
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boot_cpu_data.family = CPU_FAMILY_SH3;
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}
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