401 lines
10 KiB
C
401 lines
10 KiB
C
// SPDX-License-Identifier: GPL-2.0-or-later
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/* backing_ops.c - query/set operations on saved SPU context.
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*
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* Copyright (C) IBM 2005
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* Author: Mark Nutter <mnutter@us.ibm.com>
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*
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* These register operations allow SPUFS to operate on saved
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* SPU contexts rather than hardware.
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*/
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#include <linux/errno.h>
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#include <linux/sched.h>
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#include <linux/kernel.h>
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#include <linux/mm.h>
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#include <linux/vmalloc.h>
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#include <linux/smp.h>
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#include <linux/stddef.h>
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#include <linux/unistd.h>
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#include <linux/poll.h>
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#include <asm/io.h>
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#include <asm/spu.h>
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#include <asm/spu_csa.h>
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#include <asm/spu_info.h>
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#include <asm/mmu_context.h>
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#include "spufs.h"
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/*
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* Reads/writes to various problem and priv2 registers require
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* state changes, i.e. generate SPU events, modify channel
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* counts, etc.
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*/
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static void gen_spu_event(struct spu_context *ctx, u32 event)
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{
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u64 ch0_cnt;
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u64 ch0_data;
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u64 ch1_data;
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ch0_cnt = ctx->csa.spu_chnlcnt_RW[0];
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ch0_data = ctx->csa.spu_chnldata_RW[0];
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ch1_data = ctx->csa.spu_chnldata_RW[1];
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ctx->csa.spu_chnldata_RW[0] |= event;
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if ((ch0_cnt == 0) && !(ch0_data & event) && (ch1_data & event)) {
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ctx->csa.spu_chnlcnt_RW[0] = 1;
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}
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}
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static int spu_backing_mbox_read(struct spu_context *ctx, u32 * data)
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{
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u32 mbox_stat;
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int ret = 0;
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spin_lock(&ctx->csa.register_lock);
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mbox_stat = ctx->csa.prob.mb_stat_R;
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if (mbox_stat & 0x0000ff) {
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/* Read the first available word.
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* Implementation note: the depth
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* of pu_mb_R is currently 1.
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*/
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*data = ctx->csa.prob.pu_mb_R;
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ctx->csa.prob.mb_stat_R &= ~(0x0000ff);
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ctx->csa.spu_chnlcnt_RW[28] = 1;
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gen_spu_event(ctx, MFC_PU_MAILBOX_AVAILABLE_EVENT);
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ret = 4;
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}
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spin_unlock(&ctx->csa.register_lock);
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return ret;
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}
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static u32 spu_backing_mbox_stat_read(struct spu_context *ctx)
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{
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return ctx->csa.prob.mb_stat_R;
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}
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static __poll_t spu_backing_mbox_stat_poll(struct spu_context *ctx,
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__poll_t events)
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{
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__poll_t ret;
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u32 stat;
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ret = 0;
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spin_lock_irq(&ctx->csa.register_lock);
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stat = ctx->csa.prob.mb_stat_R;
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/* if the requested event is there, return the poll
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mask, otherwise enable the interrupt to get notified,
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but first mark any pending interrupts as done so
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we don't get woken up unnecessarily */
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if (events & (EPOLLIN | EPOLLRDNORM)) {
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if (stat & 0xff0000)
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ret |= EPOLLIN | EPOLLRDNORM;
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else {
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ctx->csa.priv1.int_stat_class2_RW &=
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~CLASS2_MAILBOX_INTR;
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ctx->csa.priv1.int_mask_class2_RW |=
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CLASS2_ENABLE_MAILBOX_INTR;
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}
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}
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if (events & (EPOLLOUT | EPOLLWRNORM)) {
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if (stat & 0x00ff00)
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ret = EPOLLOUT | EPOLLWRNORM;
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else {
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ctx->csa.priv1.int_stat_class2_RW &=
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~CLASS2_MAILBOX_THRESHOLD_INTR;
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ctx->csa.priv1.int_mask_class2_RW |=
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CLASS2_ENABLE_MAILBOX_THRESHOLD_INTR;
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}
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}
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spin_unlock_irq(&ctx->csa.register_lock);
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return ret;
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}
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static int spu_backing_ibox_read(struct spu_context *ctx, u32 * data)
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{
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int ret;
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spin_lock(&ctx->csa.register_lock);
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if (ctx->csa.prob.mb_stat_R & 0xff0000) {
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/* Read the first available word.
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* Implementation note: the depth
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* of puint_mb_R is currently 1.
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*/
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*data = ctx->csa.priv2.puint_mb_R;
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ctx->csa.prob.mb_stat_R &= ~(0xff0000);
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ctx->csa.spu_chnlcnt_RW[30] = 1;
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gen_spu_event(ctx, MFC_PU_INT_MAILBOX_AVAILABLE_EVENT);
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ret = 4;
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} else {
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/* make sure we get woken up by the interrupt */
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ctx->csa.priv1.int_mask_class2_RW |= CLASS2_ENABLE_MAILBOX_INTR;
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ret = 0;
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}
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spin_unlock(&ctx->csa.register_lock);
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return ret;
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}
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static int spu_backing_wbox_write(struct spu_context *ctx, u32 data)
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{
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int ret;
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spin_lock(&ctx->csa.register_lock);
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if ((ctx->csa.prob.mb_stat_R) & 0x00ff00) {
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int slot = ctx->csa.spu_chnlcnt_RW[29];
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int avail = (ctx->csa.prob.mb_stat_R & 0x00ff00) >> 8;
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/* We have space to write wbox_data.
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* Implementation note: the depth
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* of spu_mb_W is currently 4.
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*/
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BUG_ON(avail != (4 - slot));
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ctx->csa.spu_mailbox_data[slot] = data;
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ctx->csa.spu_chnlcnt_RW[29] = ++slot;
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ctx->csa.prob.mb_stat_R &= ~(0x00ff00);
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ctx->csa.prob.mb_stat_R |= (((4 - slot) & 0xff) << 8);
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gen_spu_event(ctx, MFC_SPU_MAILBOX_WRITTEN_EVENT);
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ret = 4;
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} else {
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/* make sure we get woken up by the interrupt when space
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becomes available */
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ctx->csa.priv1.int_mask_class2_RW |=
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CLASS2_ENABLE_MAILBOX_THRESHOLD_INTR;
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ret = 0;
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}
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spin_unlock(&ctx->csa.register_lock);
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return ret;
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}
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static u32 spu_backing_signal1_read(struct spu_context *ctx)
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{
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return ctx->csa.spu_chnldata_RW[3];
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}
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static void spu_backing_signal1_write(struct spu_context *ctx, u32 data)
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{
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spin_lock(&ctx->csa.register_lock);
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if (ctx->csa.priv2.spu_cfg_RW & 0x1)
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ctx->csa.spu_chnldata_RW[3] |= data;
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else
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ctx->csa.spu_chnldata_RW[3] = data;
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ctx->csa.spu_chnlcnt_RW[3] = 1;
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gen_spu_event(ctx, MFC_SIGNAL_1_EVENT);
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spin_unlock(&ctx->csa.register_lock);
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}
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static u32 spu_backing_signal2_read(struct spu_context *ctx)
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{
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return ctx->csa.spu_chnldata_RW[4];
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}
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static void spu_backing_signal2_write(struct spu_context *ctx, u32 data)
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{
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spin_lock(&ctx->csa.register_lock);
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if (ctx->csa.priv2.spu_cfg_RW & 0x2)
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ctx->csa.spu_chnldata_RW[4] |= data;
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else
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ctx->csa.spu_chnldata_RW[4] = data;
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ctx->csa.spu_chnlcnt_RW[4] = 1;
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gen_spu_event(ctx, MFC_SIGNAL_2_EVENT);
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spin_unlock(&ctx->csa.register_lock);
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}
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static void spu_backing_signal1_type_set(struct spu_context *ctx, u64 val)
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{
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u64 tmp;
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spin_lock(&ctx->csa.register_lock);
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tmp = ctx->csa.priv2.spu_cfg_RW;
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if (val)
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tmp |= 1;
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else
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tmp &= ~1;
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ctx->csa.priv2.spu_cfg_RW = tmp;
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spin_unlock(&ctx->csa.register_lock);
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}
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static u64 spu_backing_signal1_type_get(struct spu_context *ctx)
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{
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return ((ctx->csa.priv2.spu_cfg_RW & 1) != 0);
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}
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static void spu_backing_signal2_type_set(struct spu_context *ctx, u64 val)
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{
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u64 tmp;
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spin_lock(&ctx->csa.register_lock);
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tmp = ctx->csa.priv2.spu_cfg_RW;
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if (val)
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tmp |= 2;
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else
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tmp &= ~2;
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ctx->csa.priv2.spu_cfg_RW = tmp;
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spin_unlock(&ctx->csa.register_lock);
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}
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static u64 spu_backing_signal2_type_get(struct spu_context *ctx)
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{
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return ((ctx->csa.priv2.spu_cfg_RW & 2) != 0);
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}
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static u32 spu_backing_npc_read(struct spu_context *ctx)
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{
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return ctx->csa.prob.spu_npc_RW;
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}
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static void spu_backing_npc_write(struct spu_context *ctx, u32 val)
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{
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ctx->csa.prob.spu_npc_RW = val;
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}
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static u32 spu_backing_status_read(struct spu_context *ctx)
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{
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return ctx->csa.prob.spu_status_R;
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}
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static char *spu_backing_get_ls(struct spu_context *ctx)
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{
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return ctx->csa.lscsa->ls;
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}
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static void spu_backing_privcntl_write(struct spu_context *ctx, u64 val)
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{
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ctx->csa.priv2.spu_privcntl_RW = val;
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}
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static u32 spu_backing_runcntl_read(struct spu_context *ctx)
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{
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return ctx->csa.prob.spu_runcntl_RW;
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}
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static void spu_backing_runcntl_write(struct spu_context *ctx, u32 val)
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{
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spin_lock(&ctx->csa.register_lock);
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ctx->csa.prob.spu_runcntl_RW = val;
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if (val & SPU_RUNCNTL_RUNNABLE) {
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ctx->csa.prob.spu_status_R &=
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~SPU_STATUS_STOPPED_BY_STOP &
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~SPU_STATUS_STOPPED_BY_HALT &
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~SPU_STATUS_SINGLE_STEP &
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~SPU_STATUS_INVALID_INSTR &
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~SPU_STATUS_INVALID_CH;
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ctx->csa.prob.spu_status_R |= SPU_STATUS_RUNNING;
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} else {
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ctx->csa.prob.spu_status_R &= ~SPU_STATUS_RUNNING;
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}
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spin_unlock(&ctx->csa.register_lock);
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}
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static void spu_backing_runcntl_stop(struct spu_context *ctx)
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{
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spu_backing_runcntl_write(ctx, SPU_RUNCNTL_STOP);
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}
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static void spu_backing_master_start(struct spu_context *ctx)
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{
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struct spu_state *csa = &ctx->csa;
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u64 sr1;
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spin_lock(&csa->register_lock);
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sr1 = csa->priv1.mfc_sr1_RW | MFC_STATE1_MASTER_RUN_CONTROL_MASK;
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csa->priv1.mfc_sr1_RW = sr1;
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spin_unlock(&csa->register_lock);
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}
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static void spu_backing_master_stop(struct spu_context *ctx)
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{
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struct spu_state *csa = &ctx->csa;
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u64 sr1;
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spin_lock(&csa->register_lock);
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sr1 = csa->priv1.mfc_sr1_RW & ~MFC_STATE1_MASTER_RUN_CONTROL_MASK;
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csa->priv1.mfc_sr1_RW = sr1;
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spin_unlock(&csa->register_lock);
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}
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static int spu_backing_set_mfc_query(struct spu_context * ctx, u32 mask,
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u32 mode)
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{
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struct spu_problem_collapsed *prob = &ctx->csa.prob;
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int ret;
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spin_lock(&ctx->csa.register_lock);
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ret = -EAGAIN;
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if (prob->dma_querytype_RW)
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goto out;
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ret = 0;
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/* FIXME: what are the side-effects of this? */
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prob->dma_querymask_RW = mask;
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prob->dma_querytype_RW = mode;
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/* In the current implementation, the SPU context is always
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* acquired in runnable state when new bits are added to the
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* mask (tagwait), so it's sufficient just to mask
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* dma_tagstatus_R with the 'mask' parameter here.
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*/
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ctx->csa.prob.dma_tagstatus_R &= mask;
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out:
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spin_unlock(&ctx->csa.register_lock);
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return ret;
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}
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static u32 spu_backing_read_mfc_tagstatus(struct spu_context * ctx)
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{
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return ctx->csa.prob.dma_tagstatus_R;
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}
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static u32 spu_backing_get_mfc_free_elements(struct spu_context *ctx)
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{
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return ctx->csa.prob.dma_qstatus_R;
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}
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static int spu_backing_send_mfc_command(struct spu_context *ctx,
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struct mfc_dma_command *cmd)
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{
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int ret;
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spin_lock(&ctx->csa.register_lock);
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ret = -EAGAIN;
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/* FIXME: set up priv2->puq */
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spin_unlock(&ctx->csa.register_lock);
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return ret;
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}
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static void spu_backing_restart_dma(struct spu_context *ctx)
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{
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ctx->csa.priv2.mfc_control_RW |= MFC_CNTL_RESTART_DMA_COMMAND;
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}
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struct spu_context_ops spu_backing_ops = {
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.mbox_read = spu_backing_mbox_read,
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.mbox_stat_read = spu_backing_mbox_stat_read,
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.mbox_stat_poll = spu_backing_mbox_stat_poll,
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.ibox_read = spu_backing_ibox_read,
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.wbox_write = spu_backing_wbox_write,
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.signal1_read = spu_backing_signal1_read,
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.signal1_write = spu_backing_signal1_write,
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.signal2_read = spu_backing_signal2_read,
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.signal2_write = spu_backing_signal2_write,
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.signal1_type_set = spu_backing_signal1_type_set,
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.signal1_type_get = spu_backing_signal1_type_get,
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.signal2_type_set = spu_backing_signal2_type_set,
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.signal2_type_get = spu_backing_signal2_type_get,
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.npc_read = spu_backing_npc_read,
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.npc_write = spu_backing_npc_write,
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.status_read = spu_backing_status_read,
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.get_ls = spu_backing_get_ls,
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.privcntl_write = spu_backing_privcntl_write,
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.runcntl_read = spu_backing_runcntl_read,
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.runcntl_write = spu_backing_runcntl_write,
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.runcntl_stop = spu_backing_runcntl_stop,
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.master_start = spu_backing_master_start,
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.master_stop = spu_backing_master_stop,
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.set_mfc_query = spu_backing_set_mfc_query,
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.read_mfc_tagstatus = spu_backing_read_mfc_tagstatus,
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.get_mfc_free_elements = spu_backing_get_mfc_free_elements,
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.send_mfc_command = spu_backing_send_mfc_command,
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.restart_dma = spu_backing_restart_dma,
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};
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