173 lines
3.6 KiB
C
173 lines
3.6 KiB
C
// SPDX-License-Identifier: GPL-2.0-only
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/*
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* PQ2 ADS-style PCI interrupt controller
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*
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* Copyright 2007 Freescale Semiconductor, Inc.
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* Author: Scott Wood <scottwood@freescale.com>
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*
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* Loosely based on mpc82xx ADS support by Vitaly Bordug <vbordug@ru.mvista.com>
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* Copyright (c) 2006 MontaVista Software, Inc.
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*/
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#include <linux/init.h>
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#include <linux/spinlock.h>
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#include <linux/irq.h>
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#include <linux/types.h>
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#include <linux/slab.h>
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#include <linux/of_irq.h>
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#include <asm/io.h>
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#include <asm/cpm2.h>
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#include "pq2.h"
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static DEFINE_RAW_SPINLOCK(pci_pic_lock);
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struct pq2ads_pci_pic {
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struct device_node *node;
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struct irq_domain *host;
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struct {
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u32 stat;
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u32 mask;
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} __iomem *regs;
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};
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#define NUM_IRQS 32
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static void pq2ads_pci_mask_irq(struct irq_data *d)
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{
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struct pq2ads_pci_pic *priv = irq_data_get_irq_chip_data(d);
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int irq = NUM_IRQS - irqd_to_hwirq(d) - 1;
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if (irq != -1) {
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unsigned long flags;
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raw_spin_lock_irqsave(&pci_pic_lock, flags);
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setbits32(&priv->regs->mask, 1 << irq);
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mb();
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raw_spin_unlock_irqrestore(&pci_pic_lock, flags);
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}
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}
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static void pq2ads_pci_unmask_irq(struct irq_data *d)
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{
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struct pq2ads_pci_pic *priv = irq_data_get_irq_chip_data(d);
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int irq = NUM_IRQS - irqd_to_hwirq(d) - 1;
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if (irq != -1) {
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unsigned long flags;
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raw_spin_lock_irqsave(&pci_pic_lock, flags);
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clrbits32(&priv->regs->mask, 1 << irq);
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raw_spin_unlock_irqrestore(&pci_pic_lock, flags);
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}
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}
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static struct irq_chip pq2ads_pci_ic = {
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.name = "PQ2 ADS PCI",
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.irq_mask = pq2ads_pci_mask_irq,
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.irq_mask_ack = pq2ads_pci_mask_irq,
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.irq_ack = pq2ads_pci_mask_irq,
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.irq_unmask = pq2ads_pci_unmask_irq,
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.irq_enable = pq2ads_pci_unmask_irq,
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.irq_disable = pq2ads_pci_mask_irq
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};
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static void pq2ads_pci_irq_demux(struct irq_desc *desc)
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{
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struct pq2ads_pci_pic *priv = irq_desc_get_handler_data(desc);
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u32 stat, mask, pend;
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int bit;
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for (;;) {
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stat = in_be32(&priv->regs->stat);
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mask = in_be32(&priv->regs->mask);
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pend = stat & ~mask;
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if (!pend)
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break;
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for (bit = 0; pend != 0; ++bit, pend <<= 1) {
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if (pend & 0x80000000)
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generic_handle_domain_irq(priv->host, bit);
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}
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}
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}
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static int pci_pic_host_map(struct irq_domain *h, unsigned int virq,
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irq_hw_number_t hw)
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{
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irq_set_status_flags(virq, IRQ_LEVEL);
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irq_set_chip_data(virq, h->host_data);
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irq_set_chip_and_handler(virq, &pq2ads_pci_ic, handle_level_irq);
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return 0;
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}
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static const struct irq_domain_ops pci_pic_host_ops = {
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.map = pci_pic_host_map,
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};
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int __init pq2ads_pci_init_irq(void)
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{
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struct pq2ads_pci_pic *priv;
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struct irq_domain *host;
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struct device_node *np;
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int ret = -ENODEV;
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int irq;
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np = of_find_compatible_node(NULL, NULL, "fsl,pq2ads-pci-pic");
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if (!np) {
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printk(KERN_ERR "No pci pic node in device tree.\n");
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goto out;
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}
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irq = irq_of_parse_and_map(np, 0);
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if (!irq) {
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printk(KERN_ERR "No interrupt in pci pic node.\n");
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goto out_put_node;
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}
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priv = kzalloc(sizeof(*priv), GFP_KERNEL);
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if (!priv) {
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ret = -ENOMEM;
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goto out_unmap_irq;
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}
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/* PCI interrupt controller registers: status and mask */
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priv->regs = of_iomap(np, 0);
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if (!priv->regs) {
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printk(KERN_ERR "Cannot map PCI PIC registers.\n");
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goto out_free_kmalloc;
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}
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/* mask all PCI interrupts */
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out_be32(&priv->regs->mask, ~0);
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mb();
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host = irq_domain_add_linear(np, NUM_IRQS, &pci_pic_host_ops, priv);
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if (!host) {
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ret = -ENOMEM;
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goto out_unmap_regs;
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}
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priv->host = host;
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irq_set_handler_data(irq, priv);
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irq_set_chained_handler(irq, pq2ads_pci_irq_demux);
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ret = 0;
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goto out_put_node;
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out_unmap_regs:
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iounmap(priv->regs);
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out_free_kmalloc:
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kfree(priv);
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out_unmap_irq:
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irq_dispose_mapping(irq);
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out_put_node:
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of_node_put(np);
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out:
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return ret;
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}
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