135 lines
5.0 KiB
C
135 lines
5.0 KiB
C
/* SPDX-License-Identifier: GPL-2.0-or-later */
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/*
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* Copyright 2016,2017 IBM Corporation.
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*/
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#ifndef _ASM_POWERPC_XIVE_REGS_H
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#define _ASM_POWERPC_XIVE_REGS_H
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/*
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* "magic" Event State Buffer (ESB) MMIO offsets.
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*
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* Each interrupt source has a 2-bit state machine called ESB
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* which can be controlled by MMIO. It's made of 2 bits, P and
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* Q. P indicates that an interrupt is pending (has been sent
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* to a queue and is waiting for an EOI). Q indicates that the
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* interrupt has been triggered while pending.
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*
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* This acts as a coalescing mechanism in order to guarantee
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* that a given interrupt only occurs at most once in a queue.
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*
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* When doing an EOI, the Q bit will indicate if the interrupt
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* needs to be re-triggered.
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*
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* The following offsets into the ESB MMIO allow to read or
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* manipulate the PQ bits. They must be used with an 8-bytes
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* load instruction. They all return the previous state of the
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* interrupt (atomically).
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*
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* Additionally, some ESB pages support doing an EOI via a
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* store at 0 and some ESBs support doing a trigger via a
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* separate trigger page.
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*/
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#define XIVE_ESB_STORE_EOI 0x400 /* Store */
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#define XIVE_ESB_LOAD_EOI 0x000 /* Load */
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#define XIVE_ESB_GET 0x800 /* Load */
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#define XIVE_ESB_SET_PQ_00 0xc00 /* Load */
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#define XIVE_ESB_SET_PQ_01 0xd00 /* Load */
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#define XIVE_ESB_SET_PQ_10 0xe00 /* Load */
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#define XIVE_ESB_SET_PQ_11 0xf00 /* Load */
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/*
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* Load-after-store ordering
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*
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* Adding this offset to the load address will enforce
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* load-after-store ordering. This is required to use StoreEOI.
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*/
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#define XIVE_ESB_LD_ST_MO 0x40 /* Load-after-store ordering */
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#define XIVE_ESB_VAL_P 0x2
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#define XIVE_ESB_VAL_Q 0x1
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#define XIVE_ESB_INVALID 0xFF
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/*
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* Thread Management (aka "TM") registers
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*/
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/* TM register offsets */
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#define TM_QW0_USER 0x000 /* All rings */
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#define TM_QW1_OS 0x010 /* Ring 0..2 */
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#define TM_QW2_HV_POOL 0x020 /* Ring 0..1 */
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#define TM_QW3_HV_PHYS 0x030 /* Ring 0..1 */
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/* Byte offsets inside a QW QW0 QW1 QW2 QW3 */
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#define TM_NSR 0x0 /* + + - + */
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#define TM_CPPR 0x1 /* - + - + */
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#define TM_IPB 0x2 /* - + + + */
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#define TM_LSMFB 0x3 /* - + + + */
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#define TM_ACK_CNT 0x4 /* - + - - */
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#define TM_INC 0x5 /* - + - + */
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#define TM_AGE 0x6 /* - + - + */
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#define TM_PIPR 0x7 /* - + - + */
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#define TM_WORD0 0x0
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#define TM_WORD1 0x4
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/*
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* QW word 2 contains the valid bit at the top and other fields
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* depending on the QW.
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*/
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#define TM_WORD2 0x8
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#define TM_QW0W2_VU PPC_BIT32(0)
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#define TM_QW0W2_LOGIC_SERV PPC_BITMASK32(1,31) // XX 2,31 ?
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#define TM_QW1W2_VO PPC_BIT32(0)
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#define TM_QW1W2_HO PPC_BIT32(1) /* P10 XIVE2 */
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#define TM_QW1W2_OS_CAM PPC_BITMASK32(8,31)
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#define TM_QW2W2_VP PPC_BIT32(0)
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#define TM_QW2W2_HP PPC_BIT32(1) /* P10 XIVE2 */
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#define TM_QW2W2_POOL_CAM PPC_BITMASK32(8,31)
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#define TM_QW3W2_VT PPC_BIT32(0)
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#define TM_QW3W2_HT PPC_BIT32(1) /* P10 XIVE2 */
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#define TM_QW3W2_LP PPC_BIT32(6)
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#define TM_QW3W2_LE PPC_BIT32(7)
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#define TM_QW3W2_T PPC_BIT32(31)
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/*
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* In addition to normal loads to "peek" and writes (only when invalid)
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* using 4 and 8 bytes accesses, the above registers support these
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* "special" byte operations:
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*
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* - Byte load from QW0[NSR] - User level NSR (EBB)
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* - Byte store to QW0[NSR] - User level NSR (EBB)
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* - Byte load/store to QW1[CPPR] and QW3[CPPR] - CPPR access
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* - Byte load from QW3[TM_WORD2] - Read VT||00000||LP||LE on thrd 0
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* otherwise VT||0000000
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* - Byte store to QW3[TM_WORD2] - Set VT bit (and LP/LE if present)
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*
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* Then we have all these "special" CI ops at these offset that trigger
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* all sorts of side effects:
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*/
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#define TM_SPC_ACK_EBB 0x800 /* Load8 ack EBB to reg*/
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#define TM_SPC_ACK_OS_REG 0x810 /* Load16 ack OS irq to reg */
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#define TM_SPC_PUSH_USR_CTX 0x808 /* Store32 Push/Validate user context */
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#define TM_SPC_PULL_USR_CTX 0x808 /* Load32 Pull/Invalidate user context */
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#define TM_SPC_SET_OS_PENDING 0x812 /* Store8 Set OS irq pending bit */
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#define TM_SPC_PULL_OS_CTX 0x818 /* Load32/Load64 Pull/Invalidate OS context to reg */
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#define TM_SPC_PULL_POOL_CTX 0x828 /* Load32/Load64 Pull/Invalidate Pool context to reg*/
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#define TM_SPC_ACK_HV_REG 0x830 /* Load16 ack HV irq to reg */
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#define TM_SPC_PULL_USR_CTX_OL 0xc08 /* Store8 Pull/Inval usr ctx to odd line */
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#define TM_SPC_ACK_OS_EL 0xc10 /* Store8 ack OS irq to even line */
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#define TM_SPC_ACK_HV_POOL_EL 0xc20 /* Store8 ack HV evt pool to even line */
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#define TM_SPC_ACK_HV_EL 0xc30 /* Store8 ack HV irq to even line */
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/* XXX more... */
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/* NSR fields for the various QW ack types */
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#define TM_QW0_NSR_EB PPC_BIT8(0)
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#define TM_QW1_NSR_EO PPC_BIT8(0)
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#define TM_QW3_NSR_HE PPC_BITMASK8(0,1)
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#define TM_QW3_NSR_HE_NONE 0
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#define TM_QW3_NSR_HE_POOL 1
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#define TM_QW3_NSR_HE_PHYS 2
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#define TM_QW3_NSR_HE_LSI 3
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#define TM_QW3_NSR_I PPC_BIT8(2)
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#define TM_QW3_NSR_GRP_LVL PPC_BIT8(3,7)
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#endif /* _ASM_POWERPC_XIVE_REGS_H */
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