709 lines
14 KiB
Plaintext
709 lines
14 KiB
Plaintext
/*
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* T4240QDS Device Tree Source
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*
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* Copyright 2012 - 2015 Freescale Semiconductor Inc.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions are met:
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* * Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* * Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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* * Neither the name of Freescale Semiconductor nor the
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* names of its contributors may be used to endorse or promote products
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* derived from this software without specific prior written permission.
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*
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*
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* ALTERNATIVELY, this software may be distributed under the terms of the
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* GNU General Public License ("GPL") as published by the Free Software
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* Foundation, either version 2 of that License or (at your option) any
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* later version.
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*
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* THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor ``AS IS'' AND ANY
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* EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
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* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
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* DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY
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* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
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* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
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* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
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* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
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* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*/
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/include/ "t4240si-pre.dtsi"
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/ {
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model = "fsl,T4240QDS";
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compatible = "fsl,T4240QDS";
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#address-cells = <2>;
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#size-cells = <2>;
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interrupt-parent = <&mpic>;
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aliases{
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phy_rgmii1 = &phyrgmii1;
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phy_rgmii2 = &phyrgmii2;
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phy_sgmii3 = &phy3;
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phy_sgmii4 = &phy4;
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phy_sgmii11 = &phy11;
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phy_sgmii12 = &phy12;
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sgmii_phy11 = &sgmiiphy11;
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sgmii_phy12 = &sgmiiphy12;
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sgmii_phy13 = &sgmiiphy13;
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sgmii_phy14 = &sgmiiphy14;
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sgmii_phy21 = &sgmiiphy21;
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sgmii_phy22 = &sgmiiphy22;
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sgmii_phy23 = &sgmiiphy23;
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sgmii_phy24 = &sgmiiphy24;
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sgmii_phy31 = &sgmiiphy31;
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sgmii_phy32 = &sgmiiphy32;
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sgmii_phy33 = &sgmiiphy33;
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sgmii_phy34 = &sgmiiphy34;
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sgmii_phy41 = &sgmiiphy41;
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sgmii_phy42 = &sgmiiphy42;
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sgmii_phy43 = &sgmiiphy43;
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sgmii_phy44 = &sgmiiphy44;
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phy_xfi1 = &xfiphy1;
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phy_xfi2 = &xfiphy2;
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phy_xfi3 = &xfiphy3;
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phy_xfi4 = &xfiphy4;
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xfi_pcs_mdio1 = &xfimdio0;
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xfi_pcs_mdio2 = &xfimdio1;
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xfi_pcs_mdio3 = &xfimdio2;
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xfi_pcs_mdio4 = &xfimdio3;
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emi1_rgmii = &t4240mdio0;
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emi1_slot1 = &t4240mdio1;
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emi1_slot2 = &t4240mdio2;
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emi1_slot3 = &t4240mdio3;
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emi1_slot4 = &t4240mdio4;
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};
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ifc: localbus@ffe124000 {
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reg = <0xf 0xfe124000 0 0x2000>;
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ranges = <0 0 0xf 0xe8000000 0x08000000
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2 0 0xf 0xff800000 0x00010000
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3 0 0xf 0xffdf0000 0x00008000>;
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nor@0,0 {
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#address-cells = <1>;
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#size-cells = <1>;
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compatible = "cfi-flash";
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reg = <0x0 0x0 0x8000000>;
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bank-width = <2>;
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device-width = <1>;
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};
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nand@2,0 {
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#address-cells = <1>;
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#size-cells = <1>;
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compatible = "fsl,ifc-nand";
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reg = <0x2 0x0 0x10000>;
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partition@0 {
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/* This location must not be altered */
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/* 1MB for u-boot Bootloader Image */
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reg = <0x0 0x00100000>;
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label = "NAND U-Boot Image";
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read-only;
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};
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partition@100000 {
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/* 1MB for DTB Image */
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reg = <0x00100000 0x00100000>;
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label = "NAND DTB Image";
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};
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partition@200000 {
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/* 10MB for Linux Kernel Image */
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reg = <0x00200000 0x00A00000>;
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label = "NAND Linux Kernel Image";
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};
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partition@C00000 {
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/* 500MB for Root file System Image */
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reg = <0x00c00000 0x1F400000>;
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label = "NAND RFS Image";
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};
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};
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board-control@3,0 {
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#address-cells = <1>;
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#size-cells = <1>;
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compatible = "fsl,t4240qds-fpga", "fsl,fpga-qixis";
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reg = <3 0 0x300>;
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ranges = <0 3 0 0x300>;
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mdio-mux-emi1 {
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#address-cells = <1>;
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#size-cells = <0>;
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compatible = "mdio-mux-mmioreg", "mdio-mux";
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mdio-parent-bus = <&mdio1>;
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reg = <0x54 1>;
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mux-mask = <0xe0>;
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t4240mdio0: mdio@0 {
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#address-cells = <1>;
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#size-cells = <0>;
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reg = <0>;
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phyrgmii1: ethernet-phy@1 {
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reg = <0x1>;
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};
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phyrgmii2: ethernet-phy@2 {
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reg = <0x2>;
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};
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};
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t4240mdio1: mdio@20 {
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#address-cells = <1>;
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#size-cells = <0>;
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reg = <0x20>;
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status = "disabled";
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phy1: ethernet-phy@0 {
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reg = <0x0>;
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};
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phy2: ethernet-phy@1 {
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reg = <0x1>;
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};
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phy3: ethernet-phy@2 {
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reg = <0x2>;
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};
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phy4: ethernet-phy@3 {
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reg = <0x3>;
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};
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sgmiiphy11: ethernet-phy@1c {
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reg = <0x1c>;
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};
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sgmiiphy12: ethernet-phy@1d {
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reg = <0x1d>;
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};
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sgmiiphy13: ethernet-phy@1e {
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reg = <0x1e>;
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};
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sgmiiphy14: ethernet-phy@1f {
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reg = <0x1f>;
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};
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};
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t4240mdio2: mdio@40 {
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#address-cells = <1>;
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#size-cells = <0>;
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reg = <0x40>;
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status = "disabled";
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phy5: ethernet-phy@4 {
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reg = <0x4>;
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};
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phy6: ethernet-phy@5 {
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reg = <0x5>;
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};
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phy7: ethernet-phy@6 {
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reg = <0x6>;
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};
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phy8: ethernet-phy@7 {
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reg = <0x7>;
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};
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sgmiiphy21: ethernet-phy@1c {
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reg = <0x1c>;
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};
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sgmiiphy22: ethernet-phy@1d {
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reg = <0x1d>;
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};
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sgmiiphy23: ethernet-phy@1e {
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reg = <0x1e>;
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};
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sgmiiphy24: ethernet-phy@1f {
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reg = <0x1f>;
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};
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};
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t4240mdio3: mdio@60 {
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#address-cells = <1>;
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#size-cells = <0>;
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reg = <0x60>;
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status = "disabled";
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phy9: ethernet-phy@8 {
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reg = <0x8>;
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};
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phy10: ethernet-phy@9 {
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reg = <0x9>;
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};
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phy11: ethernet-phy@a {
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reg = <0xa>;
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};
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phy12: ethernet-phy@b {
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reg = <0xb>;
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};
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sgmiiphy31: ethernet-phy@1c {
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reg = <0x1c>;
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};
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sgmiiphy32: ethernet-phy@1d {
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reg = <0x1d>;
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};
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sgmiiphy33: ethernet-phy@1e {
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reg = <0x1e>;
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};
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sgmiiphy34: ethernet-phy@1f {
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reg = <0x1f>;
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};
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};
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t4240mdio4: mdio@80 {
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#address-cells = <1>;
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#size-cells = <0>;
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reg = <0x80>;
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status = "disabled";
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phy13: ethernet-phy@c {
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reg = <0xc>;
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};
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phy14: ethernet-phy@d {
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reg = <0xd>;
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};
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phy15: ethernet-phy@e {
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reg = <0xe>;
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};
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phy16: ethernet-phy@f {
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reg = <0xf>;
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};
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sgmiiphy41: ethernet-phy@1c {
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reg = <0x1c>;
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};
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sgmiiphy42: ethernet-phy@1d {
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reg = <0x1d>;
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};
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sgmiiphy43: ethernet-phy@1e {
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reg = <0x1e>;
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};
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sgmiiphy44: ethernet-phy@1f {
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reg = <0x1f>;
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};
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};
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};
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};
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};
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memory {
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device_type = "memory";
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};
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reserved-memory {
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#address-cells = <2>;
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#size-cells = <2>;
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ranges;
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bman_fbpr: bman-fbpr {
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size = <0 0x1000000>;
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alignment = <0 0x1000000>;
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};
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qman_fqd: qman-fqd {
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size = <0 0x400000>;
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alignment = <0 0x400000>;
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};
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qman_pfdr: qman-pfdr {
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size = <0 0x2000000>;
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alignment = <0 0x2000000>;
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};
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};
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dcsr: dcsr@f00000000 {
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ranges = <0x00000000 0xf 0x00000000 0x01072000>;
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};
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bportals: bman-portals@ff4000000 {
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ranges = <0x0 0xf 0xf4000000 0x2000000>;
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};
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qportals: qman-portals@ff6000000 {
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ranges = <0x0 0xf 0xf6000000 0x2000000>;
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};
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soc: soc@ffe000000 {
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ranges = <0x00000000 0xf 0xfe000000 0x1000000>;
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reg = <0xf 0xfe000000 0 0x00001000>;
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spi@110000 {
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flash@0 {
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#address-cells = <1>;
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#size-cells = <1>;
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compatible = "sst,sst25wf040", "jedec,spi-nor";
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reg = <0>;
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spi-max-frequency = <40000000>; /* input clock */
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};
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};
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i2c@118000 {
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mux@77 {
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compatible = "nxp,pca9547";
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reg = <0x77>;
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#address-cells = <1>;
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#size-cells = <0>;
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i2c@0 {
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#address-cells = <1>;
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#size-cells = <0>;
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reg = <0>;
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eeprom@51 {
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compatible = "atmel,24c256";
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reg = <0x51>;
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};
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eeprom@52 {
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compatible = "atmel,24c256";
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reg = <0x52>;
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};
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eeprom@53 {
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compatible = "atmel,24c256";
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reg = <0x53>;
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};
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eeprom@54 {
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compatible = "atmel,24c256";
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reg = <0x54>;
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};
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eeprom@55 {
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compatible = "atmel,24c256";
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reg = <0x55>;
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};
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eeprom@56 {
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compatible = "atmel,24c256";
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reg = <0x56>;
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};
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rtc@68 {
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compatible = "dallas,ds3232";
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reg = <0x68>;
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interrupts = <0x1 0x1 0 0>;
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};
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};
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i2c@2 {
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#address-cells = <1>;
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#size-cells = <0>;
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reg = <0x2>;
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ina220@40 {
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compatible = "ti,ina220";
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reg = <0x40>;
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shunt-resistor = <1000>;
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};
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ina220@41 {
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compatible = "ti,ina220";
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reg = <0x41>;
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shunt-resistor = <1000>;
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};
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ina220@44 {
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compatible = "ti,ina220";
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reg = <0x44>;
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shunt-resistor = <1000>;
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};
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ina220@45 {
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compatible = "ti,ina220";
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reg = <0x45>;
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shunt-resistor = <1000>;
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};
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ina220@46 {
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compatible = "ti,ina220";
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reg = <0x46>;
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shunt-resistor = <1000>;
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};
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ina220@47 {
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compatible = "ti,ina220";
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reg = <0x47>;
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shunt-resistor = <1000>;
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};
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};
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};
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};
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sdhc@114000 {
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voltage-ranges = <1800 1800 3300 3300>;
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};
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fman@400000 {
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port@83000 {
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status = "disabled";
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};
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port@84000 {
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status = "disabled";
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};
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port@85000 {
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status = "disabled";
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};
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port@86000 {
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status = "disabled";
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};
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port@87000 {
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status = "disabled";
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};
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ethernet@e0000 {
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phy-handle = <&phy5>;
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phy-connection-type = "sgmii";
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};
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ethernet@e2000 {
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phy-handle = <&phy6>;
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phy-connection-type = "sgmii";
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};
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ethernet@e4000 {
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phy-handle = <&phy7>;
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phy-connection-type = "sgmii";
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};
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ethernet@e6000 {
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phy-handle = <&phy8>;
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phy-connection-type = "sgmii";
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};
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ethernet@e8000 {
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phy-handle = <&phyrgmii2>;
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phy-connection-type = "rgmii";
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};
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ethernet@ea000 {
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phy-handle = <&phy2>;
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phy-connection-type = "sgmii";
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};
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ethernet@f0000 {
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phy-handle = <&xauiphy1>;
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phy-connection-type = "xgmii";
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};
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ethernet@f2000 {
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phy-handle = <&xauiphy2>;
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phy-connection-type = "xgmii";
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};
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xfimdio0: mdio@f1000 {
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status = "disabled";
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xfiphy1: ethernet-phy@0 {
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compatible = "ethernet-phy-ieee802.3-c45";
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reg = <0x0>;
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};
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};
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xfimdio1: mdio@f3000 {
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status = "disabled";
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xfiphy2: ethernet-phy@0 {
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compatible = "ethernet-phy-ieee802.3-c45";
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reg = <0x0>;
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};
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};
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};
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fman@500000 {
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port@84000 {
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status = "disabled";
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};
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port@85000 {
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status = "disabled";
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};
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port@86000 {
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status = "disabled";
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};
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port@87000 {
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status = "disabled";
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};
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ethernet@e0000 {
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phy-handle = <&phy13>;
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phy-connection-type = "sgmii";
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};
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ethernet@e2000 {
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phy-handle = <&phy14>;
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phy-connection-type = "sgmii";
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};
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ethernet@e4000 {
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phy-handle = <&phy15>;
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phy-connection-type = "sgmii";
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};
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ethernet@e6000 {
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phy-handle = <&phy16>;
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phy-connection-type = "sgmii";
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};
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ethernet@e8000 {
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phy-handle = <&phyrgmii1>;
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phy-connection-type = "rgmii";
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};
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ethernet@ea000 {
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phy-handle = <&phy10>;
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|
phy-connection-type = "sgmii";
|
|
};
|
|
|
|
ethernet@f0000 {
|
|
phy-handle = <&xauiphy3>;
|
|
phy-connection-type = "xgmii";
|
|
};
|
|
|
|
ethernet@f2000 {
|
|
phy-handle = <&xauiphy4>;
|
|
phy-connection-type = "xgmii";
|
|
};
|
|
|
|
xfimdio2: mdio@f1000 {
|
|
status = "disabled";
|
|
|
|
xfiphy3: ethernet-phy@0 {
|
|
compatible = "ethernet-phy-ieee802.3-c45";
|
|
reg = <0x0>;
|
|
};
|
|
};
|
|
|
|
xfimdio3: mdio@f3000 {
|
|
status = "disabled";
|
|
|
|
xfiphy4: ethernet-phy@0 {
|
|
compatible = "ethernet-phy-ieee802.3-c45";
|
|
reg = <0x0>;
|
|
};
|
|
};
|
|
|
|
mdio@fd000 {
|
|
xauiphy1: ethernet-phy@0 {
|
|
compatible = "ethernet-phy-ieee802.3-c45";
|
|
reg = <0x0>;
|
|
};
|
|
|
|
xauiphy2: ethernet-phy@1 {
|
|
compatible = "ethernet-phy-ieee802.3-c45";
|
|
reg = <0x1>;
|
|
};
|
|
|
|
xauiphy3: ethernet-phy@2 {
|
|
compatible = "ethernet-phy-ieee802.3-c45";
|
|
reg = <0x2>;
|
|
};
|
|
|
|
xauiphy4: ethernet-phy@3 {
|
|
compatible = "ethernet-phy-ieee802.3-c45";
|
|
reg = <0x3>;
|
|
};
|
|
};
|
|
};
|
|
};
|
|
|
|
pci0: pcie@ffe240000 {
|
|
reg = <0xf 0xfe240000 0 0x10000>;
|
|
ranges = <0x02000000 0 0xe0000000 0xc 0x00000000 0x0 0x20000000
|
|
0x01000000 0 0x00000000 0xf 0xf8000000 0x0 0x00010000>;
|
|
pcie@0 {
|
|
ranges = <0x02000000 0 0xe0000000
|
|
0x02000000 0 0xe0000000
|
|
0 0x20000000
|
|
|
|
0x01000000 0 0x00000000
|
|
0x01000000 0 0x00000000
|
|
0 0x00010000>;
|
|
};
|
|
};
|
|
|
|
pci1: pcie@ffe250000 {
|
|
reg = <0xf 0xfe250000 0 0x10000>;
|
|
ranges = <0x02000000 0x0 0xe0000000 0xc 0x20000000 0x0 0x20000000
|
|
0x01000000 0x0 0x00000000 0xf 0xf8010000 0x0 0x00010000>;
|
|
pcie@0 {
|
|
ranges = <0x02000000 0 0xe0000000
|
|
0x02000000 0 0xe0000000
|
|
0 0x20000000
|
|
|
|
0x01000000 0 0x00000000
|
|
0x01000000 0 0x00000000
|
|
0 0x00010000>;
|
|
};
|
|
};
|
|
|
|
pci2: pcie@ffe260000 {
|
|
reg = <0xf 0xfe260000 0 0x1000>;
|
|
ranges = <0x02000000 0 0xe0000000 0xc 0x40000000 0 0x20000000
|
|
0x01000000 0 0x00000000 0xf 0xf8020000 0 0x00010000>;
|
|
pcie@0 {
|
|
ranges = <0x02000000 0 0xe0000000
|
|
0x02000000 0 0xe0000000
|
|
0 0x20000000
|
|
|
|
0x01000000 0 0x00000000
|
|
0x01000000 0 0x00000000
|
|
0 0x00010000>;
|
|
};
|
|
};
|
|
|
|
pci3: pcie@ffe270000 {
|
|
reg = <0xf 0xfe270000 0 0x10000>;
|
|
ranges = <0x02000000 0 0xe0000000 0xc 0x60000000 0 0x20000000
|
|
0x01000000 0 0x00000000 0xf 0xf8030000 0 0x00010000>;
|
|
pcie@0 {
|
|
ranges = <0x02000000 0 0xe0000000
|
|
0x02000000 0 0xe0000000
|
|
0 0x20000000
|
|
|
|
0x01000000 0 0x00000000
|
|
0x01000000 0 0x00000000
|
|
0 0x00010000>;
|
|
};
|
|
};
|
|
rio: rapidio@ffe0c0000 {
|
|
reg = <0xf 0xfe0c0000 0 0x11000>;
|
|
|
|
port1 {
|
|
ranges = <0 0 0xc 0x20000000 0 0x10000000>;
|
|
};
|
|
port2 {
|
|
ranges = <0 0 0xc 0x30000000 0 0x10000000>;
|
|
};
|
|
};
|
|
};
|
|
|
|
/include/ "t4240si-post.dtsi"
|