201 lines
2.6 KiB
Plaintext
201 lines
2.6 KiB
Plaintext
// SPDX-License-Identifier: GPL-2.0+
|
|
/*
|
|
* dts file for Xilinx ZynqMP zc1751-xm018-dc4
|
|
*
|
|
* (C) Copyright 2015 - 2021, Xilinx, Inc.
|
|
*
|
|
* Michal Simek <michal.simek@xilinx.com>
|
|
*/
|
|
|
|
/dts-v1/;
|
|
|
|
#include "zynqmp.dtsi"
|
|
#include "zynqmp-clk-ccf.dtsi"
|
|
|
|
/ {
|
|
model = "ZynqMP zc1751-xm018-dc4";
|
|
compatible = "xlnx,zynqmp-zc1751", "xlnx,zynqmp";
|
|
|
|
aliases {
|
|
ethernet0 = &gem0;
|
|
ethernet1 = &gem1;
|
|
ethernet2 = &gem2;
|
|
ethernet3 = &gem3;
|
|
i2c0 = &i2c0;
|
|
i2c1 = &i2c1;
|
|
rtc0 = &rtc;
|
|
serial0 = &uart0;
|
|
serial1 = &uart1;
|
|
spi0 = &qspi;
|
|
};
|
|
|
|
chosen {
|
|
bootargs = "earlycon";
|
|
stdout-path = "serial0:115200n8";
|
|
};
|
|
|
|
memory@0 {
|
|
device_type = "memory";
|
|
reg = <0x0 0x0 0x0 0x80000000>, <0x8 0x00000000 0x0 0x80000000>;
|
|
};
|
|
};
|
|
|
|
&can0 {
|
|
status = "okay";
|
|
};
|
|
|
|
&can1 {
|
|
status = "okay";
|
|
};
|
|
|
|
&fpd_dma_chan1 {
|
|
status = "okay";
|
|
};
|
|
|
|
&fpd_dma_chan2 {
|
|
status = "okay";
|
|
};
|
|
|
|
&fpd_dma_chan3 {
|
|
status = "okay";
|
|
};
|
|
|
|
&fpd_dma_chan4 {
|
|
status = "okay";
|
|
};
|
|
|
|
&fpd_dma_chan5 {
|
|
status = "okay";
|
|
};
|
|
|
|
&fpd_dma_chan6 {
|
|
status = "okay";
|
|
};
|
|
|
|
&fpd_dma_chan7 {
|
|
status = "okay";
|
|
};
|
|
|
|
&fpd_dma_chan8 {
|
|
status = "okay";
|
|
};
|
|
|
|
&lpd_dma_chan1 {
|
|
status = "okay";
|
|
};
|
|
|
|
&lpd_dma_chan2 {
|
|
status = "okay";
|
|
};
|
|
|
|
&lpd_dma_chan3 {
|
|
status = "okay";
|
|
};
|
|
|
|
&lpd_dma_chan4 {
|
|
status = "okay";
|
|
};
|
|
|
|
&lpd_dma_chan5 {
|
|
status = "okay";
|
|
};
|
|
|
|
&lpd_dma_chan6 {
|
|
status = "okay";
|
|
};
|
|
|
|
&lpd_dma_chan7 {
|
|
status = "okay";
|
|
};
|
|
|
|
&lpd_dma_chan8 {
|
|
status = "okay";
|
|
};
|
|
|
|
&gem0 {
|
|
status = "okay";
|
|
phy-mode = "rgmii-id";
|
|
phy-handle = <ðernet_phy0>;
|
|
ethernet_phy0: ethernet-phy@0 { /* Marvell 88e1512 */
|
|
reg = <0>;
|
|
};
|
|
ethernet_phy7: ethernet-phy@7 { /* Vitesse VSC8211 */
|
|
reg = <7>;
|
|
};
|
|
ethernet_phy3: ethernet-phy@3 { /* Realtek RTL8211DN */
|
|
reg = <3>;
|
|
};
|
|
ethernet_phy8: ethernet-phy@8 { /* Vitesse VSC8211 */
|
|
reg = <8>;
|
|
};
|
|
};
|
|
|
|
&gem1 {
|
|
status = "okay";
|
|
phy-mode = "rgmii-id";
|
|
phy-handle = <ðernet_phy7>;
|
|
};
|
|
|
|
&gem2 {
|
|
status = "okay";
|
|
phy-mode = "rgmii-id";
|
|
phy-handle = <ðernet_phy3>;
|
|
};
|
|
|
|
&gem3 {
|
|
status = "okay";
|
|
phy-mode = "rgmii-id";
|
|
phy-handle = <ðernet_phy8>;
|
|
};
|
|
|
|
&gpio {
|
|
status = "okay";
|
|
};
|
|
|
|
&i2c0 {
|
|
clock-frequency = <400000>;
|
|
status = "okay";
|
|
};
|
|
|
|
&i2c1 {
|
|
clock-frequency = <400000>;
|
|
status = "okay";
|
|
};
|
|
|
|
&qspi {
|
|
status = "okay";
|
|
flash@0 {
|
|
compatible = "m25p80", "jedec,spi-nor"; /* 32MB */
|
|
#address-cells = <1>;
|
|
#size-cells = <1>;
|
|
reg = <0x0>;
|
|
spi-tx-bus-width = <1>;
|
|
spi-rx-bus-width = <4>; /* also DUAL configuration possible */
|
|
spi-max-frequency = <108000000>; /* Based on DC1 spec */
|
|
};
|
|
};
|
|
|
|
&rtc {
|
|
status = "okay";
|
|
};
|
|
|
|
&uart0 {
|
|
status = "okay";
|
|
};
|
|
|
|
&uart1 {
|
|
status = "okay";
|
|
};
|
|
|
|
&watchdog0 {
|
|
status = "okay";
|
|
};
|
|
|
|
&zynqmp_dpdma {
|
|
status = "okay";
|
|
};
|
|
|
|
&zynqmp_dpsub {
|
|
status = "okay";
|
|
};
|