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linuxdebug/arch/arm64/boot/dts/tesla/fsd.dtsi

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// SPDX-License-Identifier: GPL-2.0
/*
* Tesla Full Self-Driving SoC device tree source
*
* Copyright (c) 2017-2022 Samsung Electronics Co., Ltd.
* https://www.samsung.com
* Copyright (c) 2017-2022 Tesla, Inc.
* https://www.tesla.com
*/
#include <dt-bindings/clock/fsd-clk.h>
#include <dt-bindings/interrupt-controller/arm-gic.h>
/ {
compatible = "tesla,fsd";
interrupt-parent = <&gic>;
#address-cells = <2>;
#size-cells = <2>;
aliases {
i2c0 = &hsi2c_0;
i2c1 = &hsi2c_1;
i2c2 = &hsi2c_2;
i2c3 = &hsi2c_3;
i2c4 = &hsi2c_4;
i2c5 = &hsi2c_5;
i2c6 = &hsi2c_6;
i2c7 = &hsi2c_7;
pinctrl0 = &pinctrl_fsys0;
pinctrl1 = &pinctrl_peric;
pinctrl2 = &pinctrl_pmu;
spi0 = &spi_0;
spi1 = &spi_1;
spi2 = &spi_2;
};
cpus {
#address-cells = <2>;
#size-cells = <0>;
cpu-map {
cluster0 {
core0 {
cpu = <&cpucl0_0>;
};
core1 {
cpu = <&cpucl0_1>;
};
core2 {
cpu = <&cpucl0_2>;
};
core3 {
cpu = <&cpucl0_3>;
};
};
cluster1 {
core0 {
cpu = <&cpucl1_0>;
};
core1 {
cpu = <&cpucl1_1>;
};
core2 {
cpu = <&cpucl1_2>;
};
core3 {
cpu = <&cpucl1_3>;
};
};
cluster2 {
core0 {
cpu = <&cpucl2_0>;
};
core1 {
cpu = <&cpucl2_1>;
};
core2 {
cpu = <&cpucl2_2>;
};
core3 {
cpu = <&cpucl2_3>;
};
};
};
/* Cluster 0 */
cpucl0_0: cpu@0 {
device_type = "cpu";
compatible = "arm,cortex-a72";
reg = <0x0 0x000>;
enable-method = "psci";
clock-frequency = <2400000000>;
cpu-idle-states = <&CPU_SLEEP>;
i-cache-size = <0xc000>;
i-cache-line-size = <64>;
i-cache-sets = <256>;
d-cache-size = <0x8000>;
d-cache-line-size = <64>;
d-cache-sets = <256>;
next-level-cache = <&cpucl_l2>;
};
cpucl0_1: cpu@1 {
device_type = "cpu";
compatible = "arm,cortex-a72";
reg = <0x0 0x001>;
enable-method = "psci";
clock-frequency = <2400000000>;
cpu-idle-states = <&CPU_SLEEP>;
i-cache-size = <0xc000>;
i-cache-line-size = <64>;
i-cache-sets = <256>;
d-cache-size = <0x8000>;
d-cache-line-size = <64>;
d-cache-sets = <256>;
next-level-cache = <&cpucl_l2>;
};
cpucl0_2: cpu@2 {
device_type = "cpu";
compatible = "arm,cortex-a72";
reg = <0x0 0x002>;
enable-method = "psci";
clock-frequency = <2400000000>;
cpu-idle-states = <&CPU_SLEEP>;
i-cache-size = <0xc000>;
i-cache-line-size = <64>;
i-cache-sets = <256>;
d-cache-size = <0x8000>;
d-cache-line-size = <64>;
d-cache-sets = <256>;
next-level-cache = <&cpucl_l2>;
};
cpucl0_3: cpu@3 {
device_type = "cpu";
compatible = "arm,cortex-a72";
reg = <0x0 0x003>;
enable-method = "psci";
cpu-idle-states = <&CPU_SLEEP>;
i-cache-size = <0xc000>;
i-cache-line-size = <64>;
i-cache-sets = <256>;
d-cache-size = <0x8000>;
d-cache-line-size = <64>;
d-cache-sets = <256>;
next-level-cache = <&cpucl_l2>;
};
/* Cluster 1 */
cpucl1_0: cpu@100 {
device_type = "cpu";
compatible = "arm,cortex-a72";
reg = <0x0 0x100>;
enable-method = "psci";
clock-frequency = <2400000000>;
cpu-idle-states = <&CPU_SLEEP>;
i-cache-size = <0xc000>;
i-cache-line-size = <64>;
i-cache-sets = <256>;
d-cache-size = <0x8000>;
d-cache-line-size = <64>;
d-cache-sets = <256>;
next-level-cache = <&cpucl_l2>;
};
cpucl1_1: cpu@101 {
device_type = "cpu";
compatible = "arm,cortex-a72";
reg = <0x0 0x101>;
enable-method = "psci";
clock-frequency = <2400000000>;
cpu-idle-states = <&CPU_SLEEP>;
i-cache-size = <0xc000>;
i-cache-line-size = <64>;
i-cache-sets = <256>;
d-cache-size = <0x8000>;
d-cache-line-size = <64>;
d-cache-sets = <256>;
next-level-cache = <&cpucl_l2>;
};
cpucl1_2: cpu@102 {
device_type = "cpu";
compatible = "arm,cortex-a72";
reg = <0x0 0x102>;
enable-method = "psci";
clock-frequency = <2400000000>;
cpu-idle-states = <&CPU_SLEEP>;
i-cache-size = <0xc000>;
i-cache-line-size = <64>;
i-cache-sets = <256>;
d-cache-size = <0x8000>;
d-cache-line-size = <64>;
d-cache-sets = <256>;
next-level-cache = <&cpucl_l2>;
};
cpucl1_3: cpu@103 {
device_type = "cpu";
compatible = "arm,cortex-a72";
reg = <0x0 0x103>;
enable-method = "psci";
clock-frequency = <2400000000>;
cpu-idle-states = <&CPU_SLEEP>;
i-cache-size = <0xc000>;
i-cache-line-size = <64>;
i-cache-sets = <256>;
d-cache-size = <0x8000>;
d-cache-line-size = <64>;
d-cache-sets = <256>;
next-level-cache = <&cpucl_l2>;
};
/* Cluster 2 */
cpucl2_0: cpu@200 {
device_type = "cpu";
compatible = "arm,cortex-a72";
reg = <0x0 0x200>;
enable-method = "psci";
clock-frequency = <2400000000>;
cpu-idle-states = <&CPU_SLEEP>;
i-cache-size = <0xc000>;
i-cache-line-size = <64>;
i-cache-sets = <256>;
d-cache-size = <0x8000>;
d-cache-line-size = <64>;
d-cache-sets = <256>;
next-level-cache = <&cpucl_l2>;
};
cpucl2_1: cpu@201 {
device_type = "cpu";
compatible = "arm,cortex-a72";
reg = <0x0 0x201>;
enable-method = "psci";
clock-frequency = <2400000000>;
cpu-idle-states = <&CPU_SLEEP>;
i-cache-size = <0xc000>;
i-cache-line-size = <64>;
i-cache-sets = <256>;
d-cache-size = <0x8000>;
d-cache-line-size = <64>;
d-cache-sets = <256>;
next-level-cache = <&cpucl_l2>;
};
cpucl2_2: cpu@202 {
device_type = "cpu";
compatible = "arm,cortex-a72";
reg = <0x0 0x202>;
enable-method = "psci";
clock-frequency = <2400000000>;
cpu-idle-states = <&CPU_SLEEP>;
i-cache-size = <0xc000>;
i-cache-line-size = <64>;
i-cache-sets = <256>;
d-cache-size = <0x8000>;
d-cache-line-size = <64>;
d-cache-sets = <256>;
next-level-cache = <&cpucl_l2>;
};
cpucl2_3: cpu@203 {
device_type = "cpu";
compatible = "arm,cortex-a72";
reg = <0x0 0x203>;
enable-method = "psci";
clock-frequency = <2400000000>;
cpu-idle-states = <&CPU_SLEEP>;
i-cache-size = <0xc000>;
i-cache-line-size = <64>;
i-cache-sets = <256>;
d-cache-size = <0x8000>;
d-cache-line-size = <64>;
d-cache-sets = <256>;
next-level-cache = <&cpucl_l2>;
};
cpucl_l2: l2-cache0 {
compatible = "cache";
cache-size = <0x400000>;
cache-line-size = <64>;
cache-sets = <4096>;
};
idle-states {
entry-method = "psci";
CPU_SLEEP: cpu-sleep {
idle-state-name = "c2";
compatible = "arm,idle-state";
local-timer-stop;
arm,psci-suspend-param = <0x0010000>;
entry-latency-us = <30>;
exit-latency-us = <75>;
min-residency-us = <300>;
};
};
};
arm-pmu {
compatible = "arm,armv8-pmuv3";
interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 359 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 370 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 371 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 372 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 373 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 384 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 385 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 386 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 387 IRQ_TYPE_LEVEL_HIGH>;
interrupt-affinity = <&cpucl0_0>, <&cpucl0_1>, <&cpucl0_2>,
<&cpucl0_3>, <&cpucl1_0>, <&cpucl1_1>,
<&cpucl1_2>, <&cpucl1_3>, <&cpucl2_0>,
<&cpucl2_1>, <&cpucl2_2>, <&cpucl2_3>;
};
psci {
compatible = "arm,psci-1.0";
method = "smc";
};
timer {
compatible = "arm,armv8-timer";
interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_LOW>,
<GIC_PPI 14 IRQ_TYPE_LEVEL_LOW>,
<GIC_PPI 11 IRQ_TYPE_LEVEL_LOW>,
<GIC_PPI 10 IRQ_TYPE_LEVEL_LOW>;
};
fin_pll: clock {
compatible = "fixed-clock";
clock-output-names = "fin_pll";
#clock-cells = <0>;
};
soc: soc@0 {
compatible = "simple-bus";
#address-cells = <2>;
#size-cells = <2>;
ranges = <0x0 0x0 0x0 0x0 0x0 0x18000000>;
dma-ranges = <0x0 0x0 0x0 0x0 0x10 0x0>;
gic: interrupt-controller@10400000 {
compatible = "arm,gic-v3";
#interrupt-cells = <3>;
interrupt-controller;
reg = <0x0 0x10400000 0x0 0x10000>, /* GICD */
<0x0 0x10600000 0x0 0x200000>; /* GICR_RD+GICR_SGI */
interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;
};
smmu_imem: iommu@10200000 {
compatible = "arm,mmu-500";
reg = <0x0 0x10200000 0x0 0x10000>;
#iommu-cells = <2>;
#global-interrupts = <7>;
interrupts = <GIC_SPI 438 IRQ_TYPE_LEVEL_HIGH>, /* Global secure fault */
<GIC_SPI 439 IRQ_TYPE_LEVEL_HIGH>, /* Global non-secure fault */
<GIC_SPI 451 IRQ_TYPE_LEVEL_HIGH>, /* Combined secure interrupt */
<GIC_SPI 450 IRQ_TYPE_LEVEL_HIGH>, /* Combined non-secure interrupt */
/* Performance counter interrupts */
<GIC_SPI 441 IRQ_TYPE_LEVEL_HIGH>, /* for FSYS1_0 */
<GIC_SPI 442 IRQ_TYPE_LEVEL_HIGH>, /* for FSYS1_1 */
<GIC_SPI 443 IRQ_TYPE_LEVEL_HIGH>, /* for IMEM_0 */
/* Per context non-secure context interrupts, 0-3 interrupts */
<GIC_SPI 446 IRQ_TYPE_LEVEL_HIGH>, /* for CONTEXT_0 */
<GIC_SPI 447 IRQ_TYPE_LEVEL_HIGH>, /* for CONTEXT_1 */
<GIC_SPI 448 IRQ_TYPE_LEVEL_HIGH>, /* for CONTEXT_2 */
<GIC_SPI 449 IRQ_TYPE_LEVEL_HIGH>; /* for CONTEXT_3 */
};
smmu_isp: iommu@12100000 {
compatible = "arm,mmu-500";
reg = <0x0 0x12100000 0x0 0x10000>;
#iommu-cells = <2>;
#global-interrupts = <11>;
interrupts = <GIC_SPI 321 IRQ_TYPE_LEVEL_HIGH>, /* Global secure fault */
<GIC_SPI 322 IRQ_TYPE_LEVEL_HIGH>, /* Global non-secure fault */
<GIC_SPI 346 IRQ_TYPE_LEVEL_HIGH>, /* Combined secure interrupt */
<GIC_SPI 345 IRQ_TYPE_LEVEL_HIGH>, /* Combined non-secure interrupt */
/* Performance counter interrupts */
<GIC_SPI 323 IRQ_TYPE_LEVEL_HIGH>, /* for CAM_CSI */
<GIC_SPI 324 IRQ_TYPE_LEVEL_HIGH>, /* for CAM_DP_0 */
<GIC_SPI 325 IRQ_TYPE_LEVEL_HIGH>, /* for CAM_DP_1 */
<GIC_SPI 326 IRQ_TYPE_LEVEL_HIGH>, /* for CAM_ISP_0 */
<GIC_SPI 327 IRQ_TYPE_LEVEL_HIGH>, /* for CAM_ISP_1 */
<GIC_SPI 328 IRQ_TYPE_LEVEL_HIGH>, /* for CAM_MFC_0 */
<GIC_SPI 329 IRQ_TYPE_LEVEL_HIGH>, /* for CAM_MFC_1 */
/* Per context non-secure context interrupts, 0-7 interrupts */
<GIC_SPI 330 IRQ_TYPE_LEVEL_HIGH>, /* for CONTEXT_0 */
<GIC_SPI 331 IRQ_TYPE_LEVEL_HIGH>, /* for CONTEXT_1 */
<GIC_SPI 332 IRQ_TYPE_LEVEL_HIGH>, /* for CONTEXT_2 */
<GIC_SPI 333 IRQ_TYPE_LEVEL_HIGH>, /* for CONTEXT_3 */
<GIC_SPI 334 IRQ_TYPE_LEVEL_HIGH>, /* for CONTEXT_4 */
<GIC_SPI 335 IRQ_TYPE_LEVEL_HIGH>, /* for CONTEXT_5 */
<GIC_SPI 336 IRQ_TYPE_LEVEL_HIGH>, /* for CONTEXT_6 */
<GIC_SPI 337 IRQ_TYPE_LEVEL_HIGH>; /* for CONTEXT_7 */
};
smmu_peric: iommu@14900000 {
compatible = "arm,mmu-500";
reg = <0x0 0x14900000 0x0 0x10000>;
#iommu-cells = <2>;
#global-interrupts = <5>;
interrupts = <GIC_SPI 197 IRQ_TYPE_LEVEL_HIGH>, /* Global secure fault */
<GIC_SPI 196 IRQ_TYPE_LEVEL_HIGH>, /* Global non-secure fault */
<GIC_SPI 193 IRQ_TYPE_LEVEL_HIGH>, /* Combined secure interrupt */
<GIC_SPI 192 IRQ_TYPE_LEVEL_HIGH>, /* Combined non-secure interrupt */
/* Performance counter interrupts */
<GIC_SPI 198 IRQ_TYPE_LEVEL_HIGH>, /* for PERIC */
/* Per context non-secure context interrupts, 0-1 interrupts */
<GIC_SPI 194 IRQ_TYPE_LEVEL_HIGH>, /* for CONTEXT_0 */
<GIC_SPI 195 IRQ_TYPE_LEVEL_HIGH>; /* for CONTEXT_1 */
};
smmu_fsys0: iommu@15450000 {
compatible = "arm,mmu-500";
reg = <0x0 0x15450000 0x0 0x10000>;
#iommu-cells = <2>;
#global-interrupts = <5>;
interrupts = <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>, /* Global secure fault */
<GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>, /* Global non-secure fault */
<GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>, /* Combined secure interrupt */
<GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>, /* Combined non-secure interrupt */
/* Performance counter interrupts */
<GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>, /* for FSYS0 */
/* Per context non-secure context interrupts, 0-1 interrupts */
<GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>, /* for CONTEXT_0 */
<GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>; /* for CONTEXT_1 */
};
clock_imem: clock-controller@10010000 {
compatible = "tesla,fsd-clock-imem";
reg = <0x0 0x10010000 0x0 0x3000>;
#clock-cells = <1>;
clocks = <&fin_pll>,
<&clock_cmu DOUT_CMU_IMEM_TCUCLK>,
<&clock_cmu DOUT_CMU_IMEM_ACLK>,
<&clock_cmu DOUT_CMU_IMEM_DMACLK>;
clock-names = "fin_pll",
"dout_cmu_imem_tcuclk",
"dout_cmu_imem_aclk",
"dout_cmu_imem_dmaclk";
};
clock_cmu: clock-controller@11c10000 {
compatible = "tesla,fsd-clock-cmu";
reg = <0x0 0x11c10000 0x0 0x3000>;
#clock-cells = <1>;
clocks = <&fin_pll>;
clock-names = "fin_pll";
};
clock_csi: clock-controller@12610000 {
compatible = "tesla,fsd-clock-cam_csi";
reg = <0x0 0x12610000 0x0 0x3000>;
#clock-cells = <1>;
clocks = <&fin_pll>;
clock-names = "fin_pll";
};
clock_mfc: clock-controller@12810000 {
compatible = "tesla,fsd-clock-mfc";
reg = <0x0 0x12810000 0x0 0x3000>;
#clock-cells = <1>;
clocks = <&fin_pll>;
clock-names = "fin_pll";
};
clock_peric: clock-controller@14010000 {
compatible = "tesla,fsd-clock-peric";
reg = <0x0 0x14010000 0x0 0x3000>;
#clock-cells = <1>;
clocks = <&fin_pll>,
<&clock_cmu DOUT_CMU_PLL_SHARED0_DIV4>,
<&clock_cmu DOUT_CMU_PERIC_SHARED1DIV36>,
<&clock_cmu DOUT_CMU_PERIC_SHARED0DIV3_TBUCLK>,
<&clock_cmu DOUT_CMU_PERIC_SHARED0DIV20>,
<&clock_cmu DOUT_CMU_PERIC_SHARED1DIV4_DMACLK>;
clock-names = "fin_pll",
"dout_cmu_pll_shared0_div4",
"dout_cmu_peric_shared1div36",
"dout_cmu_peric_shared0div3_tbuclk",
"dout_cmu_peric_shared0div20",
"dout_cmu_peric_shared1div4_dmaclk";
};
clock_fsys0: clock-controller@15010000 {
compatible = "tesla,fsd-clock-fsys0";
reg = <0x0 0x15010000 0x0 0x3000>;
#clock-cells = <1>;
clocks = <&fin_pll>,
<&clock_cmu DOUT_CMU_PLL_SHARED0_DIV6>,
<&clock_cmu DOUT_CMU_FSYS0_SHARED1DIV4>,
<&clock_cmu DOUT_CMU_FSYS0_SHARED0DIV4>;
clock-names = "fin_pll",
"dout_cmu_pll_shared0_div6",
"dout_cmu_fsys0_shared1div4",
"dout_cmu_fsys0_shared0div4";
};
clock_fsys1: clock-controller@16810000 {
compatible = "tesla,fsd-clock-fsys1";
reg = <0x0 0x16810000 0x0 0x3000>;
#clock-cells = <1>;
clocks = <&fin_pll>,
<&clock_cmu DOUT_CMU_FSYS1_SHARED0DIV8>,
<&clock_cmu DOUT_CMU_FSYS1_SHARED0DIV4>;
clock-names = "fin_pll",
"dout_cmu_fsys1_shared0div8",
"dout_cmu_fsys1_shared0div4";
};
mdma0: dma-controller@10100000 {
compatible = "arm,pl330", "arm,primecell";
reg = <0x0 0x10100000 0x0 0x1000>;
interrupts = <GIC_SPI 424 IRQ_TYPE_LEVEL_HIGH>;
#dma-cells = <1>;
clocks = <&clock_imem IMEM_DMA0_IPCLKPORT_ACLK>;
clock-names = "apb_pclk";
iommus = <&smmu_imem 0x800 0x0>;
};
mdma1: dma-controller@10110000 {
compatible = "arm,pl330", "arm,primecell";
reg = <0x0 0x10110000 0x0 0x1000>;
interrupts = <GIC_SPI 425 IRQ_TYPE_LEVEL_HIGH>;
#dma-cells = <1>;
clocks = <&clock_imem IMEM_DMA1_IPCLKPORT_ACLK>;
clock-names = "apb_pclk";
iommus = <&smmu_imem 0x801 0x0>;
};
pdma0: dma-controller@14280000 {
compatible = "arm,pl330", "arm,primecell";
reg = <0x0 0x14280000 0x0 0x1000>;
interrupts = <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>;
#dma-cells = <1>;
clocks = <&clock_peric PERIC_DMA0_IPCLKPORT_ACLK>;
clock-names = "apb_pclk";
iommus = <&smmu_peric 0x2 0x0>;
};
pdma1: dma-controller@14290000 {
compatible = "arm,pl330", "arm,primecell";
reg = <0x0 0x14290000 0x0 0x1000>;
interrupts = <GIC_SPI 191 IRQ_TYPE_LEVEL_HIGH>;
#dma-cells = <1>;
clocks = <&clock_peric PERIC_DMA1_IPCLKPORT_ACLK>;
clock-names = "apb_pclk";
iommus = <&smmu_peric 0x1 0x0>;
};
serial_0: serial@14180000 {
compatible = "samsung,exynos4210-uart";
reg = <0x0 0x14180000 0x0 0x100>;
interrupts = <GIC_SPI 171 IRQ_TYPE_LEVEL_HIGH>;
dmas = <&pdma1 1>, <&pdma1 0>;
dma-names = "rx", "tx";
clocks = <&clock_peric PERIC_PCLK_UART0>,
<&clock_peric PERIC_SCLK_UART0>;
clock-names = "uart", "clk_uart_baud0";
status = "disabled";
};
serial_1: serial@14190000 {
compatible = "samsung,exynos4210-uart";
reg = <0x0 0x14190000 0x0 0x100>;
interrupts = <GIC_SPI 172 IRQ_TYPE_LEVEL_HIGH>;
dmas = <&pdma1 3>, <&pdma1 2>;
dma-names = "rx", "tx";
clocks = <&clock_peric PERIC_PCLK_UART1>,
<&clock_peric PERIC_SCLK_UART1>;
clock-names = "uart", "clk_uart_baud0";
status = "disabled";
};
pmu_system_controller: system-controller@11400000 {
compatible = "samsung,exynos7-pmu", "syscon";
reg = <0x0 0x11400000 0x0 0x5000>;
};
watchdog_0: watchdog@100a0000 {
compatible = "samsung,exynos7-wdt";
reg = <0x0 0x100a0000 0x0 0x100>;
interrupts = <GIC_SPI 471 IRQ_TYPE_LEVEL_HIGH>;
samsung,syscon-phandle = <&pmu_system_controller>;
clocks = <&fin_pll>;
clock-names = "watchdog";
};
watchdog_1: watchdog@100b0000 {
compatible = "samsung,exynos7-wdt";
reg = <0x0 0x100b0000 0x0 0x100>;
interrupts = <GIC_SPI 472 IRQ_TYPE_LEVEL_HIGH>;
samsung,syscon-phandle = <&pmu_system_controller>;
clocks = <&fin_pll>;
clock-names = "watchdog";
};
watchdog_2: watchdog@100c0000 {
compatible = "samsung,exynos7-wdt";
reg = <0x0 0x100c0000 0x0 0x100>;
interrupts = <GIC_SPI 473 IRQ_TYPE_LEVEL_HIGH>;
samsung,syscon-phandle = <&pmu_system_controller>;
clocks = <&fin_pll>;
clock-names = "watchdog";
};
pwm_0: pwm@14100000 {
compatible = "samsung,exynos4210-pwm";
reg = <0x0 0x14100000 0x0 0x100>;
samsung,pwm-outputs = <0>, <1>, <2>, <3>;
#pwm-cells = <3>;
clocks = <&clock_peric PERIC_PWM0_IPCLKPORT_I_PCLK_S0>;
clock-names = "timers";
status = "disabled";
};
pwm_1: pwm@14110000 {
compatible = "samsung,exynos4210-pwm";
reg = <0x0 0x14110000 0x0 0x100>;
samsung,pwm-outputs = <0>, <1>, <2>, <3>;
#pwm-cells = <3>;
clocks = <&clock_peric PERIC_PWM1_IPCLKPORT_I_PCLK_S0>;
clock-names = "timers";
status = "disabled";
};
hsi2c_0: i2c@14200000 {
compatible = "samsung,exynos7-hsi2c";
reg = <0x0 0x14200000 0x0 0x1000>;
interrupts = <GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>;
#address-cells = <1>;
#size-cells = <0>;
pinctrl-names = "default";
pinctrl-0 = <&hs_i2c0_bus>;
clocks = <&clock_peric PERIC_PCLK_HSI2C0>;
clock-names = "hsi2c";
status = "disabled";
};
hsi2c_1: i2c@14210000 {
compatible = "samsung,exynos7-hsi2c";
reg = <0x0 0x14210000 0x0 0x1000>;
interrupts = <GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>;
#address-cells = <1>;
#size-cells = <0>;
pinctrl-names = "default";
pinctrl-0 = <&hs_i2c1_bus>;
clocks = <&clock_peric PERIC_PCLK_HSI2C1>;
clock-names = "hsi2c";
status = "disabled";
};
hsi2c_2: i2c@14220000 {
compatible = "samsung,exynos7-hsi2c";
reg = <0x0 0x14220000 0x0 0x1000>;
interrupts = <GIC_SPI 150 IRQ_TYPE_LEVEL_HIGH>;
#address-cells = <1>;
#size-cells = <0>;
pinctrl-names = "default";
pinctrl-0 = <&hs_i2c2_bus>;
clocks = <&clock_peric PERIC_PCLK_HSI2C2>;
clock-names = "hsi2c";
status = "disabled";
};
hsi2c_3: i2c@14230000 {
compatible = "samsung,exynos7-hsi2c";
reg = <0x0 0x14230000 0x0 0x1000>;
interrupts = <GIC_SPI 151 IRQ_TYPE_LEVEL_HIGH>;
#address-cells = <1>;
#size-cells = <0>;
pinctrl-names = "default";
pinctrl-0 = <&hs_i2c3_bus>;
clocks = <&clock_peric PERIC_PCLK_HSI2C3>;
clock-names = "hsi2c";
status = "disabled";
};
hsi2c_4: i2c@14240000 {
compatible = "samsung,exynos7-hsi2c";
reg = <0x0 0x14240000 0x0 0x1000>;
interrupts = <GIC_SPI 152 IRQ_TYPE_LEVEL_HIGH>;
#address-cells = <1>;
#size-cells = <0>;
pinctrl-names = "default";
pinctrl-0 = <&hs_i2c4_bus>;
clocks = <&clock_peric PERIC_PCLK_HSI2C4>;
clock-names = "hsi2c";
status = "disabled";
};
hsi2c_5: i2c@14250000 {
compatible = "samsung,exynos7-hsi2c";
reg = <0x0 0x14250000 0x0 0x1000>;
interrupts = <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>;
#address-cells = <1>;
#size-cells = <0>;
pinctrl-names = "default";
pinctrl-0 = <&hs_i2c5_bus>;
clocks = <&clock_peric PERIC_PCLK_HSI2C5>;
clock-names = "hsi2c";
status = "disabled";
};
hsi2c_6: i2c@14260000 {
compatible = "samsung,exynos7-hsi2c";
reg = <0x0 0x14260000 0x0 0x1000>;
interrupts = <GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>;
#address-cells = <1>;
#size-cells = <0>;
pinctrl-names = "default";
pinctrl-0 = <&hs_i2c6_bus>;
clocks = <&clock_peric PERIC_PCLK_HSI2C6>;
clock-names = "hsi2c";
status = "disabled";
};
hsi2c_7: i2c@14270000 {
compatible = "samsung,exynos7-hsi2c";
reg = <0x0 0x14270000 0x0 0x1000>;
interrupts = <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>;
#address-cells = <1>;
#size-cells = <0>;
pinctrl-names = "default";
pinctrl-0 = <&hs_i2c7_bus>;
clocks = <&clock_peric PERIC_PCLK_HSI2C7>;
clock-names = "hsi2c";
status = "disabled";
};
pinctrl_pmu: pinctrl@114f0000 {
compatible = "tesla,fsd-pinctrl";
reg = <0x0 0x114f0000 0x0 0x1000>;
};
pinctrl_peric: pinctrl@141f0000 {
compatible = "tesla,fsd-pinctrl";
reg = <0x0 0x141f0000 0x0 0x1000>;
interrupts = <GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH>;
};
pinctrl_fsys0: pinctrl@15020000 {
compatible = "tesla,fsd-pinctrl";
reg = <0x0 0x15020000 0x0 0x1000>;
interrupts = <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>;
};
spi_0: spi@14140000 {
compatible = "tesla,fsd-spi";
reg = <0x0 0x14140000 0x0 0x100>;
interrupts = <GIC_SPI 156 IRQ_TYPE_LEVEL_HIGH>;
dmas = <&pdma1 4>, <&pdma1 5>;
dma-names = "tx", "rx";
#address-cells = <1>;
#size-cells = <0>;
clocks = <&clock_peric PERIC_PCLK_SPI0>,
<&clock_peric PERIC_SCLK_SPI0>;
clock-names = "spi", "spi_busclk0";
samsung,spi-src-clk = <0>;
pinctrl-names = "default";
pinctrl-0 = <&spi0_bus>;
num-cs = <1>;
status = "disabled";
};
spi_1: spi@14150000 {
compatible = "tesla,fsd-spi";
reg = <0x0 0x14150000 0x0 0x100>;
interrupts = <GIC_SPI 157 IRQ_TYPE_LEVEL_HIGH>;
dmas = <&pdma1 6>, <&pdma1 7>;
dma-names = "tx", "rx";
#address-cells = <1>;
#size-cells = <0>;
clocks = <&clock_peric PERIC_PCLK_SPI1>,
<&clock_peric PERIC_SCLK_SPI1>;
clock-names = "spi", "spi_busclk0";
samsung,spi-src-clk = <0>;
pinctrl-names = "default";
pinctrl-0 = <&spi1_bus>;
num-cs = <1>;
status = "disabled";
};
spi_2: spi@14160000 {
compatible = "tesla,fsd-spi";
reg = <0x0 0x14160000 0x0 0x100>;
interrupts = <GIC_SPI 158 IRQ_TYPE_LEVEL_HIGH>;
dmas = <&pdma1 8>, <&pdma1 9>;
dma-names = "tx", "rx";
#address-cells = <1>;
#size-cells = <0>;
clocks = <&clock_peric PERIC_PCLK_SPI2>,
<&clock_peric PERIC_SCLK_SPI2>;
clock-names = "spi", "spi_busclk0";
samsung,spi-src-clk = <0>;
pinctrl-names = "default";
pinctrl-0 = <&spi2_bus>;
num-cs = <1>;
status = "disabled";
};
timer@10040000 {
compatible = "tesla,fsd-mct", "samsung,exynos4210-mct";
reg = <0x0 0x10040000 0x0 0x800>;
interrupts = <GIC_SPI 455 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 456 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 457 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 458 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 459 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 460 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 461 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 462 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 463 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 464 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 465 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 466 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 467 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 468 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 469 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 470 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&fin_pll>, <&clock_imem IMEM_MCT_PCLK>;
clock-names = "fin_pll", "mct";
};
ufs: ufs@15120000 {
compatible = "tesla,fsd-ufs";
reg = <0x0 0x15120000 0x0 0x200>, /* 0: HCI standard */
<0x0 0x15121100 0x0 0x200>, /* 1: Vendor specified */
<0x0 0x15110000 0x0 0x8000>, /* 2: UNIPRO */
<0x0 0x15130000 0x0 0x100>; /* 3: UFS protector */
reg-names = "hci", "vs_hci", "unipro", "ufsp";
interrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clock_fsys0 UFS0_TOP0_HCLK_BUS>,
<&clock_fsys0 UFS0_TOP0_CLK_UNIPRO>;
clock-names = "core_clk", "sclk_unipro_main";
freq-table-hz = <0 0>, <0 0>;
pinctrl-names = "default";
pinctrl-0 = <&ufs_rst_n &ufs_refclk_out>;
phys = <&ufs_phy>;
phy-names = "ufs-phy";
status = "disabled";
};
ufs_phy: ufs-phy@15124000 {
compatible = "tesla,fsd-ufs-phy";
reg = <0x0 0x15124000 0x0 0x800>;
reg-names = "phy-pma";
samsung,pmu-syscon = <&pmu_system_controller>;
#phy-cells = <0>;
clocks = <&clock_fsys0 UFS0_MPHY_REFCLK_IXTAL26>;
clock-names = "ref_clk";
};
};
};
#include "fsd-pinctrl.dtsi"
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