175 lines
3.1 KiB
Plaintext
175 lines
3.1 KiB
Plaintext
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
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/*
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* Google Cheza board device tree source
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*
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* Copyright 2018 Google LLC.
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*/
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/dts-v1/;
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#include "sdm845-cheza.dtsi"
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/ {
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model = "Google Cheza (rev3+)";
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compatible = "google,cheza", "qcom,sdm845";
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};
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/* PINCTRL - board-specific pinctrl */
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&tlmm {
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gpio-line-names = "AP_SPI_FP_MISO",
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"AP_SPI_FP_MOSI",
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"AP_SPI_FP_CLK",
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"AP_SPI_FP_CS_L",
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"UART_AP_TX_DBG_RX",
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"UART_DBG_TX_AP_RX",
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"BRIJ_SUSPEND",
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"FP_RST_L",
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"FCAM_EN",
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"",
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"EDP_BRIJ_IRQ",
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"EC_IN_RW_ODL",
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"",
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"RCAM_MCLK",
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"FCAM_MCLK",
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"",
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"RCAM_EN",
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"CCI0_SDA",
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"CCI0_SCL",
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"CCI1_SDA",
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"CCI1_SCL",
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"FCAM_RST_L",
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"FPMCU_BOOT0",
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"PEN_RST_L",
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"PEN_IRQ_L",
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"FPMCU_SEL_OD",
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"RCAM_VSYNC",
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"ESIM_MISO",
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"ESIM_MOSI",
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"ESIM_CLK",
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"ESIM_CS_L",
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"AP_PEN_1V8_SDA",
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"AP_PEN_1V8_SCL",
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"AP_TS_I2C_SDA",
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"AP_TS_I2C_SCL",
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"RCAM_RST_L",
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"",
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"AP_EDP_BKLTEN",
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"AP_BRD_ID0",
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"BOOT_CONFIG_4",
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"AMP_IRQ_L",
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"EDP_BRIJ_I2C_SDA",
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"EDP_BRIJ_I2C_SCL",
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"EN_PP3300_DX_EDP",
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"SD_CD_ODL",
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"BT_UART_RTS",
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"BT_UART_CTS",
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"BT_UART_RXD",
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"BT_UART_TXD",
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"AMP_I2C_SDA",
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"AMP_I2C_SCL",
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"AP_BRD_ID2",
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"",
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"AP_EC_SPI_CLK",
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"AP_EC_SPI_CS_L",
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"AP_EC_SPI_MISO",
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"AP_EC_SPI_MOSI",
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"FORCED_USB_BOOT",
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"AMP_BCLK",
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"AMP_LRCLK",
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"AMP_DOUT",
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"AMP_DIN",
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"AP_BRD_ID1",
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"PEN_PDCT_L",
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"HP_MCLK",
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"HP_BCLK",
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"HP_LRCLK",
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"HP_DOUT",
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"HP_DIN",
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"",
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"",
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"",
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"",
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"BT_SLIMBUS_DATA",
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"BT_SLIMBUS_CLK",
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"AMP_RESET_L",
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"",
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"FCAM_VSYNC",
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"",
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"AP_SKU_ID0",
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"EC_WOV_BCLK",
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"EC_WOV_LRCLK",
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"EC_WOV_DOUT",
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"",
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"",
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"AP_H1_SPI_MISO",
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"AP_H1_SPI_MOSI",
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"AP_H1_SPI_CLK",
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"AP_H1_SPI_CS_L",
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"",
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"AP_SPI_CS0_L",
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"AP_SPI_MOSI",
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"AP_SPI_MISO",
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"",
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"",
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"AP_SPI_CLK",
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"",
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"RFFE6_CLK",
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"RFFE6_DATA",
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"BOOT_CONFIG_1",
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"BOOT_CONFIG_2",
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"BOOT_CONFIG_0",
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"EDP_BRIJ_EN",
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"",
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"USB_HS_TX_EN",
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"UIM2_DATA",
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"UIM2_CLK",
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"UIM2_RST",
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"UIM2_PRESENT",
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"UIM1_DATA",
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"UIM1_CLK",
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"UIM1_RST",
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"",
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"AP_SKU_ID1",
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"SDM_GRFC_8",
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"SDM_GRFC_9",
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"AP_RST_REQ",
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"HP_IRQ",
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"TS_RESET_L",
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"PEN_EJECT_ODL",
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"HUB_RST_L",
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"FP_TO_AP_IRQ",
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"AP_EC_INT_L",
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"",
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"",
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"TS_INT_L",
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"AP_SUSPEND_L",
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"SDM_GRFC_3",
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/*
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* AP_FLASH_WP_L is crossystem ABI. Rev3 schematics
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* call it BIOS_FLASH_WP_R_L.
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*/
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"AP_FLASH_WP_L",
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"H1_AP_INT_ODL",
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"QLINK_REQ",
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"QLINK_EN",
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"SDM_GRFC_2",
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"BOOT_CONFIG_3",
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"WMSS_RESET_L",
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"SDM_GRFC_0",
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"SDM_GRFC_1",
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"RFFE3_DATA",
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"RFFE3_CLK",
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"RFFE4_DATA",
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"RFFE4_CLK",
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"RFFE5_DATA",
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"RFFE5_CLK",
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"GNSS_EN",
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"WCI2_LTE_COEX_RXD",
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"WCI2_LTE_COEX_TXD",
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"AP_RAM_ID0",
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"AP_RAM_ID1",
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"RFFE1_DATA",
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"RFFE1_CLK";
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};
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