313 lines
8.3 KiB
Plaintext
313 lines
8.3 KiB
Plaintext
// SPDX-License-Identifier: (GPL-2.0 OR MIT)
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/*
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* Copyright (C) 2021 MediaTek Inc.
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* Author: Sam.Shih <sam.shih@mediatek.com>
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*/
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#include <dt-bindings/interrupt-controller/irq.h>
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#include <dt-bindings/interrupt-controller/arm-gic.h>
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#include <dt-bindings/clock/mt7986-clk.h>
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#include <dt-bindings/reset/mt7986-resets.h>
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/ {
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interrupt-parent = <&gic>;
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#address-cells = <2>;
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#size-cells = <2>;
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clk40m: oscillator-40m {
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compatible = "fixed-clock";
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clock-frequency = <40000000>;
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#clock-cells = <0>;
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clock-output-names = "clkxtal";
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};
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cpus {
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#address-cells = <1>;
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#size-cells = <0>;
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cpu0: cpu@0 {
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device_type = "cpu";
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compatible = "arm,cortex-a53";
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enable-method = "psci";
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reg = <0x0>;
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#cooling-cells = <2>;
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};
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cpu1: cpu@1 {
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device_type = "cpu";
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compatible = "arm,cortex-a53";
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enable-method = "psci";
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reg = <0x1>;
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#cooling-cells = <2>;
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};
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cpu2: cpu@2 {
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device_type = "cpu";
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compatible = "arm,cortex-a53";
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enable-method = "psci";
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reg = <0x2>;
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#cooling-cells = <2>;
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};
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cpu3: cpu@3 {
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device_type = "cpu";
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enable-method = "psci";
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compatible = "arm,cortex-a53";
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reg = <0x3>;
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#cooling-cells = <2>;
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};
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};
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psci {
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compatible = "arm,psci-0.2";
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method = "smc";
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};
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reserved-memory {
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#address-cells = <2>;
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#size-cells = <2>;
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ranges;
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/* 192 KiB reserved for ARM Trusted Firmware (BL31) */
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secmon_reserved: secmon@43000000 {
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reg = <0 0x43000000 0 0x30000>;
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no-map;
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};
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wmcpu_emi: wmcpu-reserved@4fc00000 {
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no-map;
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reg = <0 0x4fc00000 0 0x00100000>;
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};
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};
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timer {
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compatible = "arm,armv8-timer";
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interrupt-parent = <&gic>;
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interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_LOW>,
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<GIC_PPI 14 IRQ_TYPE_LEVEL_LOW>,
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<GIC_PPI 11 IRQ_TYPE_LEVEL_LOW>,
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<GIC_PPI 10 IRQ_TYPE_LEVEL_LOW>;
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};
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soc {
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#address-cells = <2>;
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#size-cells = <2>;
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compatible = "simple-bus";
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ranges;
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gic: interrupt-controller@c000000 {
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compatible = "arm,gic-v3";
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#interrupt-cells = <3>;
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interrupt-parent = <&gic>;
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interrupt-controller;
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reg = <0 0x0c000000 0 0x10000>, /* GICD */
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<0 0x0c080000 0 0x80000>, /* GICR */
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<0 0x0c400000 0 0x2000>, /* GICC */
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<0 0x0c410000 0 0x1000>, /* GICH */
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<0 0x0c420000 0 0x2000>; /* GICV */
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interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;
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};
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infracfg: infracfg@10001000 {
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compatible = "mediatek,mt7986-infracfg", "syscon";
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reg = <0 0x10001000 0 0x1000>;
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#clock-cells = <1>;
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};
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wed_pcie: wed-pcie@10003000 {
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compatible = "mediatek,mt7986-wed-pcie",
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"syscon";
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reg = <0 0x10003000 0 0x10>;
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};
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topckgen: topckgen@1001b000 {
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compatible = "mediatek,mt7986-topckgen", "syscon";
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reg = <0 0x1001B000 0 0x1000>;
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#clock-cells = <1>;
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};
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watchdog: watchdog@1001c000 {
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compatible = "mediatek,mt7986-wdt";
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reg = <0 0x1001c000 0 0x1000>;
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interrupts = <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>;
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#reset-cells = <1>;
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status = "disabled";
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};
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apmixedsys: apmixedsys@1001e000 {
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compatible = "mediatek,mt7986-apmixedsys";
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reg = <0 0x1001E000 0 0x1000>;
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#clock-cells = <1>;
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};
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pio: pinctrl@1001f000 {
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compatible = "mediatek,mt7986a-pinctrl";
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reg = <0 0x1001f000 0 0x1000>,
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<0 0x11c30000 0 0x1000>,
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<0 0x11c40000 0 0x1000>,
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<0 0x11e20000 0 0x1000>,
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<0 0x11e30000 0 0x1000>,
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<0 0x11f00000 0 0x1000>,
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<0 0x11f10000 0 0x1000>,
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<0 0x1000b000 0 0x1000>;
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reg-names = "gpio", "iocfg_rt", "iocfg_rb", "iocfg_lt",
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"iocfg_lb", "iocfg_tr", "iocfg_tl", "eint";
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gpio-controller;
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#gpio-cells = <2>;
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gpio-ranges = <&pio 0 0 100>;
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interrupt-controller;
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interrupts = <GIC_SPI 225 IRQ_TYPE_LEVEL_HIGH>;
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interrupt-parent = <&gic>;
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#interrupt-cells = <2>;
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};
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sgmiisys0: syscon@10060000 {
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compatible = "mediatek,mt7986-sgmiisys_0",
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"syscon";
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reg = <0 0x10060000 0 0x1000>;
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#clock-cells = <1>;
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};
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sgmiisys1: syscon@10070000 {
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compatible = "mediatek,mt7986-sgmiisys_1",
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"syscon";
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reg = <0 0x10070000 0 0x1000>;
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#clock-cells = <1>;
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};
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trng: rng@1020f000 {
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compatible = "mediatek,mt7986-rng",
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"mediatek,mt7623-rng";
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reg = <0 0x1020f000 0 0x100>;
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clocks = <&infracfg CLK_INFRA_TRNG_CK>;
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clock-names = "rng";
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status = "disabled";
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};
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uart0: serial@11002000 {
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compatible = "mediatek,mt7986-uart",
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"mediatek,mt6577-uart";
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reg = <0 0x11002000 0 0x400>;
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interrupts = <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&infracfg CLK_INFRA_UART0_SEL>,
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<&infracfg CLK_INFRA_UART0_CK>;
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clock-names = "baud", "bus";
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assigned-clocks = <&topckgen CLK_TOP_UART_SEL>,
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<&infracfg CLK_INFRA_UART0_SEL>;
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assigned-clock-parents = <&topckgen CLK_TOP_XTAL>,
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<&topckgen CLK_TOP_UART_SEL>;
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status = "disabled";
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};
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uart1: serial@11003000 {
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compatible = "mediatek,mt7986-uart",
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"mediatek,mt6577-uart";
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reg = <0 0x11003000 0 0x400>;
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interrupts = <GIC_SPI 124 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&infracfg CLK_INFRA_UART1_SEL>,
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<&infracfg CLK_INFRA_UART1_CK>;
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clock-names = "baud", "bus";
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assigned-clocks = <&infracfg CLK_INFRA_UART1_SEL>;
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assigned-clock-parents = <&topckgen CLK_TOP_F26M_SEL>;
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status = "disabled";
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};
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uart2: serial@11004000 {
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compatible = "mediatek,mt7986-uart",
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"mediatek,mt6577-uart";
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reg = <0 0x11004000 0 0x400>;
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interrupts = <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&infracfg CLK_INFRA_UART2_SEL>,
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<&infracfg CLK_INFRA_UART2_CK>;
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clock-names = "baud", "bus";
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assigned-clocks = <&infracfg CLK_INFRA_UART2_SEL>;
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assigned-clock-parents = <&topckgen CLK_TOP_F26M_SEL>;
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status = "disabled";
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};
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ethsys: syscon@15000000 {
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#address-cells = <1>;
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#size-cells = <1>;
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compatible = "mediatek,mt7986-ethsys",
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"syscon";
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reg = <0 0x15000000 0 0x1000>;
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#clock-cells = <1>;
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#reset-cells = <1>;
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};
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wed0: wed@15010000 {
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compatible = "mediatek,mt7986-wed",
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"syscon";
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reg = <0 0x15010000 0 0x1000>;
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interrupt-parent = <&gic>;
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interrupts = <GIC_SPI 205 IRQ_TYPE_LEVEL_HIGH>;
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};
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wed1: wed@15011000 {
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compatible = "mediatek,mt7986-wed",
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"syscon";
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reg = <0 0x15011000 0 0x1000>;
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interrupt-parent = <&gic>;
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interrupts = <GIC_SPI 206 IRQ_TYPE_LEVEL_HIGH>;
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};
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eth: ethernet@15100000 {
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compatible = "mediatek,mt7986-eth";
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reg = <0 0x15100000 0 0x80000>;
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interrupts = <GIC_SPI 196 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 197 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 198 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 199 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <ðsys CLK_ETH_FE_EN>,
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<ðsys CLK_ETH_GP2_EN>,
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<ðsys CLK_ETH_GP1_EN>,
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<ðsys CLK_ETH_WOCPU1_EN>,
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<ðsys CLK_ETH_WOCPU0_EN>,
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<&sgmiisys0 CLK_SGMII0_TX250M_EN>,
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<&sgmiisys0 CLK_SGMII0_RX250M_EN>,
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<&sgmiisys0 CLK_SGMII0_CDR_REF>,
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<&sgmiisys0 CLK_SGMII0_CDR_FB>,
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<&sgmiisys1 CLK_SGMII1_TX250M_EN>,
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<&sgmiisys1 CLK_SGMII1_RX250M_EN>,
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<&sgmiisys1 CLK_SGMII1_CDR_REF>,
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<&sgmiisys1 CLK_SGMII1_CDR_FB>,
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<&topckgen CLK_TOP_NETSYS_SEL>,
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<&topckgen CLK_TOP_NETSYS_500M_SEL>;
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clock-names = "fe", "gp2", "gp1", "wocpu1", "wocpu0",
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"sgmii_tx250m", "sgmii_rx250m",
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"sgmii_cdr_ref", "sgmii_cdr_fb",
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"sgmii2_tx250m", "sgmii2_rx250m",
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"sgmii2_cdr_ref", "sgmii2_cdr_fb",
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"netsys0", "netsys1";
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assigned-clocks = <&topckgen CLK_TOP_NETSYS_2X_SEL>,
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<&topckgen CLK_TOP_SGM_325M_SEL>;
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assigned-clock-parents = <&apmixedsys CLK_APMIXED_NET2PLL>,
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<&apmixedsys CLK_APMIXED_SGMPLL>;
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mediatek,ethsys = <ðsys>;
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mediatek,sgmiisys = <&sgmiisys0>, <&sgmiisys1>;
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mediatek,wed-pcie = <&wed_pcie>;
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mediatek,wed = <&wed0>, <&wed1>;
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#reset-cells = <1>;
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#address-cells = <1>;
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#size-cells = <0>;
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status = "disabled";
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};
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wifi: wifi@18000000 {
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compatible = "mediatek,mt7986-wmac";
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resets = <&watchdog MT7986_TOPRGU_CONSYS_SW_RST>;
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reset-names = "consys";
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clocks = <&topckgen CLK_TOP_CONN_MCUSYS_SEL>,
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<&topckgen CLK_TOP_AP2CNN_HOST_SEL>;
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clock-names = "mcu", "ap2conn";
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reg = <0 0x18000000 0 0x1000000>,
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<0 0x10003000 0 0x1000>,
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<0 0x11d10000 0 0x1000>;
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interrupts = <GIC_SPI 213 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 214 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 215 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 216 IRQ_TYPE_LEVEL_HIGH>;
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memory-region = <&wmcpu_emi>;
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};
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};
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};
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