707 lines
25 KiB
Plaintext
707 lines
25 KiB
Plaintext
// SPDX-License-Identifier: GPL-2.0
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/*
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* pinctrl dts fils for Hislicon HiKey development board
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*
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*/
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#include <dt-bindings/pinctrl/hisi.h>
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/ {
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soc {
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pmx0: pinmux@f7010000 {
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pinctrl-names = "default";
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pinctrl-0 = <
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&boot_sel_pmx_func
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&hkadc_ssi_pmx_func
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&codec_clk_pmx_func
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&pwm_in_pmx_func
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&bl_pwm_pmx_func
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>;
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boot_sel_pmx_func: boot_sel_pmx_func {
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pinctrl-single,pins = <
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0x0 MUX_M0 /* BOOT_SEL (IOMG000) */
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>;
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};
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emmc_pmx_func: emmc_pmx_func {
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pinctrl-single,pins = <
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0x100 MUX_M0 /* EMMC_CLK (IOMG064) */
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0x104 MUX_M0 /* EMMC_CMD (IOMG065) */
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0x108 MUX_M0 /* EMMC_DATA0 (IOMG066) */
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0x10c MUX_M0 /* EMMC_DATA1 (IOMG067) */
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0x110 MUX_M0 /* EMMC_DATA2 (IOMG068) */
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0x114 MUX_M0 /* EMMC_DATA3 (IOMG069) */
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0x118 MUX_M0 /* EMMC_DATA4 (IOMG070) */
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0x11c MUX_M0 /* EMMC_DATA5 (IOMG071) */
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0x120 MUX_M0 /* EMMC_DATA6 (IOMG072) */
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0x124 MUX_M0 /* EMMC_DATA7 (IOMG073) */
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>;
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};
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sd_pmx_func: sd_pmx_func {
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pinctrl-single,pins = <
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0xc MUX_M0 /* SD_CLK (IOMG003) */
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0x10 MUX_M0 /* SD_CMD (IOMG004) */
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0x14 MUX_M0 /* SD_DATA0 (IOMG005) */
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0x18 MUX_M0 /* SD_DATA1 (IOMG006) */
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0x1c MUX_M0 /* SD_DATA2 (IOMG007) */
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0x20 MUX_M0 /* SD_DATA3 (IOMG008) */
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>;
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};
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sd_pmx_idle: sd_pmx_idle {
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pinctrl-single,pins = <
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0xc MUX_M1 /* SD_CLK (IOMG003) */
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0x10 MUX_M1 /* SD_CMD (IOMG004) */
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0x14 MUX_M1 /* SD_DATA0 (IOMG005) */
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0x18 MUX_M1 /* SD_DATA1 (IOMG006) */
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0x1c MUX_M1 /* SD_DATA2 (IOMG007) */
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0x20 MUX_M1 /* SD_DATA3 (IOMG008) */
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>;
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};
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sdio_pmx_func: sdio_pmx_func {
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pinctrl-single,pins = <
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0x128 MUX_M0 /* SDIO_CLK (IOMG074) */
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0x12c MUX_M0 /* SDIO_CMD (IOMG075) */
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0x130 MUX_M0 /* SDIO_DATA0 (IOMG076) */
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0x134 MUX_M0 /* SDIO_DATA1 (IOMG077) */
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0x138 MUX_M0 /* SDIO_DATA2 (IOMG078) */
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0x13c MUX_M0 /* SDIO_DATA3 (IOMG079) */
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>;
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};
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sdio_pmx_idle: sdio_pmx_idle {
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pinctrl-single,pins = <
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0x128 MUX_M1 /* SDIO_CLK (IOMG074) */
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0x12c MUX_M1 /* SDIO_CMD (IOMG075) */
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0x130 MUX_M1 /* SDIO_DATA0 (IOMG076) */
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0x134 MUX_M1 /* SDIO_DATA1 (IOMG077) */
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0x138 MUX_M1 /* SDIO_DATA2 (IOMG078) */
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0x13c MUX_M1 /* SDIO_DATA3 (IOMG079) */
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>;
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};
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isp_pmx_func: isp_pmx_func {
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pinctrl-single,pins = <
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0x24 MUX_M0 /* ISP_PWDN0 (IOMG009) */
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0x28 MUX_M0 /* ISP_PWDN1 (IOMG010) */
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0x2c MUX_M0 /* ISP_PWDN2 (IOMG011) */
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0x30 MUX_M1 /* ISP_SHUTTER0 (IOMG012) */
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0x34 MUX_M1 /* ISP_SHUTTER1 (IOMG013) */
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0x38 MUX_M1 /* ISP_PWM (IOMG014) */
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0x3c MUX_M0 /* ISP_CCLK0 (IOMG015) */
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0x40 MUX_M0 /* ISP_CCLK1 (IOMG016) */
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0x44 MUX_M0 /* ISP_RESETB0 (IOMG017) */
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0x48 MUX_M0 /* ISP_RESETB1 (IOMG018) */
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0x4c MUX_M1 /* ISP_STROBE0 (IOMG019) */
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0x50 MUX_M1 /* ISP_STROBE1 (IOMG020) */
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0x54 MUX_M0 /* ISP_SDA0 (IOMG021) */
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0x58 MUX_M0 /* ISP_SCL0 (IOMG022) */
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0x5c MUX_M0 /* ISP_SDA1 (IOMG023) */
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0x60 MUX_M0 /* ISP_SCL1 (IOMG024) */
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>;
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};
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hkadc_ssi_pmx_func: hkadc_ssi_pmx_func {
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pinctrl-single,pins = <
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0x68 MUX_M0 /* HKADC_SSI (IOMG026) */
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>;
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};
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codec_clk_pmx_func: codec_clk_pmx_func {
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pinctrl-single,pins = <
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0x6c MUX_M0 /* CODEC_CLK (IOMG027) */
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>;
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};
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codec_pmx_func: codec_pmx_func {
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pinctrl-single,pins = <
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0x70 MUX_M1 /* DMIC_CLK (IOMG028) */
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0x74 MUX_M0 /* CODEC_SYNC (IOMG029) */
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0x78 MUX_M0 /* CODEC_DI (IOMG030) */
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0x7c MUX_M0 /* CODEC_DO (IOMG031) */
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>;
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};
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fm_pmx_func: fm_pmx_func {
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pinctrl-single,pins = <
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0x80 MUX_M1 /* FM_XCLK (IOMG032) */
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0x84 MUX_M1 /* FM_XFS (IOMG033) */
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0x88 MUX_M1 /* FM_DI (IOMG034) */
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0x8c MUX_M1 /* FM_DO (IOMG035) */
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>;
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};
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bt_pmx_func: bt_pmx_func {
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pinctrl-single,pins = <
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0x90 MUX_M0 /* BT_XCLK (IOMG036) */
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0x94 MUX_M0 /* BT_XFS (IOMG037) */
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0x98 MUX_M0 /* BT_DI (IOMG038) */
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0x9c MUX_M0 /* BT_DO (IOMG039) */
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>;
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};
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pwm_in_pmx_func: pwm_in_pmx_func {
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pinctrl-single,pins = <
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0xb8 MUX_M1 /* PWM_IN (IOMG046) */
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>;
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};
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bl_pwm_pmx_func: bl_pwm_pmx_func {
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pinctrl-single,pins = <
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0xbc MUX_M1 /* BL_PWM (IOMG047) */
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>;
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};
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uart0_pmx_func: uart0_pmx_func {
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pinctrl-single,pins = <
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0xc0 MUX_M0 /* UART0_RXD (IOMG048) */
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0xc4 MUX_M0 /* UART0_TXD (IOMG049) */
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>;
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};
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uart1_pmx_func: uart1_pmx_func {
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pinctrl-single,pins = <
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0xc8 MUX_M0 /* UART1_CTS_N (IOMG050) */
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0xcc MUX_M0 /* UART1_RTS_N (IOMG051) */
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0xd0 MUX_M0 /* UART1_RXD (IOMG052) */
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0xd4 MUX_M0 /* UART1_TXD (IOMG053) */
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>;
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};
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uart2_pmx_func: uart2_pmx_func {
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pinctrl-single,pins = <
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0xd8 MUX_M0 /* UART2_CTS_N (IOMG054) */
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0xdc MUX_M0 /* UART2_RTS_N (IOMG055) */
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0xe0 MUX_M0 /* UART2_RXD (IOMG056) */
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0xe4 MUX_M0 /* UART2_TXD (IOMG057) */
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>;
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};
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uart3_pmx_func: uart3_pmx_func {
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pinctrl-single,pins = <
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0x180 MUX_M1 /* UART3_CTS_N (IOMG096) */
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0x184 MUX_M1 /* UART3_RTS_N (IOMG097) */
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0x188 MUX_M1 /* UART3_RXD (IOMG098) */
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0x18c MUX_M1 /* UART3_TXD (IOMG099) */
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>;
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};
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uart4_pmx_func: uart4_pmx_func {
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pinctrl-single,pins = <
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0x1d0 MUX_M1 /* UART4_CTS_N (IOMG116) */
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0x1d4 MUX_M1 /* UART4_RTS_N (IOMG117) */
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0x1d8 MUX_M1 /* UART4_RXD (IOMG118) */
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0x1dc MUX_M1 /* UART4_TXD (IOMG119) */
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>;
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};
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uart5_pmx_func: uart5_pmx_func {
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pinctrl-single,pins = <
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0x1c8 MUX_M1 /* UART5_RXD (IOMG114) */
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0x1cc MUX_M1 /* UART5_TXD (IOMG115) */
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>;
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};
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i2c0_pmx_func: i2c0_pmx_func {
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pinctrl-single,pins = <
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0xe8 MUX_M0 /* I2C0_SCL (IOMG058) */
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0xec MUX_M0 /* I2C0_SDA (IOMG059) */
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>;
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};
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i2c1_pmx_func: i2c1_pmx_func {
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pinctrl-single,pins = <
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0xf0 MUX_M0 /* I2C1_SCL (IOMG060) */
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0xf4 MUX_M0 /* I2C1_SDA (IOMG061) */
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>;
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};
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i2c2_pmx_func: i2c2_pmx_func {
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pinctrl-single,pins = <
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0xf8 MUX_M0 /* I2C2_SCL (IOMG062) */
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0xfc MUX_M0 /* I2C2_SDA (IOMG063) */
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>;
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};
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spi0_pmx_func: spi0_pmx_func {
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pinctrl-single,pins = <
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0x1a0 MUX_M1 /* SPI0_DI (IOMG104) */
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0x1a4 MUX_M1 /* SPI0_DO (IOMG105) */
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0x1a8 MUX_M1 /* SPI0_CS_N (IOMG106) */
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0x1ac MUX_M1 /* SPI0_CLK (IOMG107) */
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>;
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};
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};
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pmx1: pinmux@f7010800 {
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pinctrl-names = "default";
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pinctrl-0 = <
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&boot_sel_cfg_func
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&hkadc_ssi_cfg_func
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&codec_clk_cfg_func
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&pwm_in_cfg_func
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&bl_pwm_cfg_func
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>;
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boot_sel_cfg_func: boot_sel_cfg_func {
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pinctrl-single,pins = <
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0x0 0x0 /* BOOT_SEL (IOCFG000) */
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>;
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pinctrl-single,bias-pulldown = <PULL_DIS PULL_DOWN PULL_DIS PULL_DOWN>;
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pinctrl-single,bias-pullup = <PULL_UP PULL_UP PULL_DIS PULL_UP>;
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pinctrl-single,drive-strength = <DRIVE1_02MA DRIVE_MASK>;
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};
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hkadc_ssi_cfg_func: hkadc_ssi_cfg_func {
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pinctrl-single,pins = <
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0x6c 0x0 /* HKADC_SSI (IOCFG027) */
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>;
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pinctrl-single,bias-pulldown = <PULL_DIS PULL_DOWN PULL_DIS PULL_DOWN>;
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pinctrl-single,bias-pullup = <PULL_DIS PULL_UP PULL_DIS PULL_UP>;
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pinctrl-single,drive-strength = <DRIVE1_02MA DRIVE_MASK>;
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};
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emmc_clk_cfg_func: emmc_clk_cfg_func {
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pinctrl-single,pins = <
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0x104 0x0 /* EMMC_CLK (IOCFG065) */
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>;
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pinctrl-single,bias-pulldown = <PULL_DIS PULL_DOWN PULL_DIS PULL_DOWN>;
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pinctrl-single,bias-pullup = <PULL_DIS PULL_UP PULL_DIS PULL_UP>;
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pinctrl-single,drive-strength = <DRIVE1_08MA DRIVE_MASK>;
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};
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emmc_cfg_func: emmc_cfg_func {
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pinctrl-single,pins = <
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0x108 0x0 /* EMMC_CMD (IOCFG066) */
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0x10c 0x0 /* EMMC_DATA0 (IOCFG067) */
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0x110 0x0 /* EMMC_DATA1 (IOCFG068) */
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0x114 0x0 /* EMMC_DATA2 (IOCFG069) */
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0x118 0x0 /* EMMC_DATA3 (IOCFG070) */
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0x11c 0x0 /* EMMC_DATA4 (IOCFG071) */
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0x120 0x0 /* EMMC_DATA5 (IOCFG072) */
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0x124 0x0 /* EMMC_DATA6 (IOCFG073) */
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0x128 0x0 /* EMMC_DATA7 (IOCFG074) */
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>;
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pinctrl-single,bias-pulldown = <PULL_DIS PULL_DOWN PULL_DIS PULL_DOWN>;
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pinctrl-single,bias-pullup = <PULL_UP PULL_UP PULL_DIS PULL_UP>;
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pinctrl-single,drive-strength = <DRIVE1_04MA DRIVE_MASK>;
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};
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emmc_rst_cfg_func: emmc_rst_cfg_func {
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pinctrl-single,pins = <
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0x12c 0x0 /* EMMC_RST_N (IOCFG075) */
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>;
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pinctrl-single,bias-pulldown = <PULL_DIS PULL_DOWN PULL_DIS PULL_DOWN>;
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pinctrl-single,bias-pullup = <PULL_DIS PULL_UP PULL_DIS PULL_UP>;
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pinctrl-single,drive-strength = <DRIVE1_04MA DRIVE_MASK>;
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};
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sd_clk_cfg_func: sd_clk_cfg_func {
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pinctrl-single,pins = <
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0xc 0x0 /* SD_CLK (IOCFG003) */
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>;
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pinctrl-single,bias-pulldown = <PULL_DIS PULL_DOWN PULL_DIS PULL_DOWN>;
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pinctrl-single,bias-pullup = <PULL_DIS PULL_UP PULL_DIS PULL_UP>;
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pinctrl-single,drive-strength = <DRIVE1_10MA DRIVE_MASK>;
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};
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sd_clk_cfg_idle: sd_clk_cfg_idle {
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pinctrl-single,pins = <
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0xc 0x0 /* SD_CLK (IOCFG003) */
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>;
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pinctrl-single,bias-pulldown = <PULL_DOWN PULL_DOWN PULL_DIS PULL_DOWN>;
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pinctrl-single,bias-pullup = <PULL_DIS PULL_UP PULL_DIS PULL_UP>;
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pinctrl-single,drive-strength = <DRIVE1_02MA DRIVE_MASK>;
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};
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sd_cfg_func: sd_cfg_func {
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pinctrl-single,pins = <
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0x10 0x0 /* SD_CMD (IOCFG004) */
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0x14 0x0 /* SD_DATA0 (IOCFG005) */
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0x18 0x0 /* SD_DATA1 (IOCFG006) */
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0x1c 0x0 /* SD_DATA2 (IOCFG007) */
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0x20 0x0 /* SD_DATA3 (IOCFG008) */
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>;
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pinctrl-single,bias-pulldown = <PULL_DIS PULL_DOWN PULL_DIS PULL_DOWN>;
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pinctrl-single,bias-pullup = <PULL_DIS PULL_UP PULL_DIS PULL_UP>;
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pinctrl-single,drive-strength = <DRIVE1_08MA DRIVE_MASK>;
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};
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sd_cfg_idle: sd_cfg_idle {
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pinctrl-single,pins = <
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0x10 0x0 /* SD_CMD (IOCFG004) */
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0x14 0x0 /* SD_DATA0 (IOCFG005) */
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0x18 0x0 /* SD_DATA1 (IOCFG006) */
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0x1c 0x0 /* SD_DATA2 (IOCFG007) */
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0x20 0x0 /* SD_DATA3 (IOCFG008) */
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>;
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pinctrl-single,bias-pulldown = <PULL_DOWN PULL_DOWN PULL_DIS PULL_DOWN>;
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pinctrl-single,bias-pullup = <PULL_DIS PULL_UP PULL_DIS PULL_UP>;
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pinctrl-single,drive-strength = <DRIVE1_02MA DRIVE_MASK>;
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};
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sdio_clk_cfg_func: sdio_clk_cfg_func {
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pinctrl-single,pins = <
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0x134 0x0 /* SDIO_CLK (IOCFG077) */
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>;
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pinctrl-single,bias-pulldown = <PULL_DIS PULL_DOWN PULL_DIS PULL_DOWN>;
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pinctrl-single,bias-pullup = <PULL_DIS PULL_UP PULL_DIS PULL_UP>;
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pinctrl-single,drive-strength = <DRIVE1_08MA DRIVE_MASK>;
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};
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sdio_clk_cfg_idle: sdio_clk_cfg_idle {
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pinctrl-single,pins = <
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0x134 0x0 /* SDIO_CLK (IOCFG077) */
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>;
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pinctrl-single,bias-pulldown = <PULL_DOWN PULL_DOWN PULL_DIS PULL_DOWN>;
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pinctrl-single,bias-pullup = <PULL_DIS PULL_UP PULL_DIS PULL_UP>;
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pinctrl-single,drive-strength = <DRIVE1_02MA DRIVE_MASK>;
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};
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sdio_cfg_func: sdio_cfg_func {
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pinctrl-single,pins = <
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0x138 0x0 /* SDIO_CMD (IOCFG078) */
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0x13c 0x0 /* SDIO_DATA0 (IOCFG079) */
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0x140 0x0 /* SDIO_DATA1 (IOCFG080) */
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0x144 0x0 /* SDIO_DATA2 (IOCFG081) */
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0x148 0x0 /* SDIO_DATA3 (IOCFG082) */
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>;
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pinctrl-single,bias-pulldown = <PULL_DIS PULL_DOWN PULL_DIS PULL_DOWN>;
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pinctrl-single,bias-pullup = <PULL_UP PULL_UP PULL_DIS PULL_UP>;
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pinctrl-single,drive-strength = <DRIVE1_04MA DRIVE_MASK>;
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};
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sdio_cfg_idle: sdio_cfg_idle {
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pinctrl-single,pins = <
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0x138 0x0 /* SDIO_CMD (IOCFG078) */
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0x13c 0x0 /* SDIO_DATA0 (IOCFG079) */
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0x140 0x0 /* SDIO_DATA1 (IOCFG080) */
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0x144 0x0 /* SDIO_DATA2 (IOCFG081) */
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0x148 0x0 /* SDIO_DATA3 (IOCFG082) */
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>;
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pinctrl-single,bias-pulldown = <PULL_DIS PULL_DOWN PULL_DIS PULL_DOWN>;
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pinctrl-single,bias-pullup = <PULL_UP PULL_UP PULL_DIS PULL_UP>;
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pinctrl-single,drive-strength = <DRIVE1_02MA DRIVE_MASK>;
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};
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isp_cfg_func1: isp_cfg_func1 {
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pinctrl-single,pins = <
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0x28 0x0 /* ISP_PWDN0 (IOCFG010) */
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0x2c 0x0 /* ISP_PWDN1 (IOCFG011) */
|
|
0x30 0x0 /* ISP_PWDN2 (IOCFG012) */
|
|
0x34 0x0 /* ISP_SHUTTER0 (IOCFG013) */
|
|
0x38 0x0 /* ISP_SHUTTER1 (IOCFG014) */
|
|
0x3c 0x0 /* ISP_PWM (IOCFG015) */
|
|
0x40 0x0 /* ISP_CCLK0 (IOCFG016) */
|
|
0x44 0x0 /* ISP_CCLK1 (IOCFG017) */
|
|
0x48 0x0 /* ISP_RESETB0 (IOCFG018) */
|
|
0x4c 0x0 /* ISP_RESETB1 (IOCFG019) */
|
|
0x50 0x0 /* ISP_STROBE0 (IOCFG020) */
|
|
0x58 0x0 /* ISP_SDA0 (IOCFG022) */
|
|
0x5c 0x0 /* ISP_SCL0 (IOCFG023) */
|
|
0x60 0x0 /* ISP_SDA1 (IOCFG024) */
|
|
0x64 0x0 /* ISP_SCL1 (IOCFG025) */
|
|
>;
|
|
pinctrl-single,bias-pulldown = <PULL_DIS PULL_DOWN PULL_DIS PULL_DOWN>;
|
|
pinctrl-single,bias-pullup = <PULL_DIS PULL_UP PULL_DIS PULL_UP>;
|
|
pinctrl-single,drive-strength = <DRIVE1_02MA DRIVE_MASK>;
|
|
};
|
|
isp_cfg_idle1: isp_cfg_idle1 {
|
|
pinctrl-single,pins = <
|
|
0x34 0x0 /* ISP_SHUTTER0 (IOCFG013) */
|
|
0x38 0x0 /* ISP_SHUTTER1 (IOCFG014) */
|
|
>;
|
|
pinctrl-single,bias-pulldown = <PULL_DOWN PULL_DOWN PULL_DIS PULL_DOWN>;
|
|
pinctrl-single,bias-pullup = <PULL_DIS PULL_UP PULL_DIS PULL_UP>;
|
|
pinctrl-single,drive-strength = <DRIVE1_02MA DRIVE_MASK>;
|
|
};
|
|
|
|
isp_cfg_func2: isp_cfg_func2 {
|
|
pinctrl-single,pins = <
|
|
0x54 0x0 /* ISP_STROBE1 (IOCFG021) */
|
|
>;
|
|
pinctrl-single,bias-pulldown = <PULL_DOWN PULL_DOWN PULL_DIS PULL_DOWN>;
|
|
pinctrl-single,bias-pullup = <PULL_DIS PULL_UP PULL_DIS PULL_UP>;
|
|
pinctrl-single,drive-strength = <DRIVE1_02MA DRIVE_MASK>;
|
|
};
|
|
|
|
codec_clk_cfg_func: codec_clk_cfg_func {
|
|
pinctrl-single,pins = <
|
|
0x70 0x0 /* CODEC_CLK (IOCFG028) */
|
|
>;
|
|
pinctrl-single,bias-pulldown = <PULL_DIS PULL_DOWN PULL_DIS PULL_DOWN>;
|
|
pinctrl-single,bias-pullup = <PULL_DIS PULL_UP PULL_DIS PULL_UP>;
|
|
pinctrl-single,drive-strength = <DRIVE1_04MA DRIVE_MASK>;
|
|
};
|
|
codec_clk_cfg_idle: codec_clk_cfg_idle {
|
|
pinctrl-single,pins = <
|
|
0x70 0x0 /* CODEC_CLK (IOCFG028) */
|
|
>;
|
|
pinctrl-single,bias-pulldown = <PULL_DIS PULL_DOWN PULL_DIS PULL_DOWN>;
|
|
pinctrl-single,bias-pullup = <PULL_DIS PULL_UP PULL_DIS PULL_UP>;
|
|
pinctrl-single,drive-strength = <DRIVE1_02MA DRIVE_MASK>;
|
|
};
|
|
|
|
codec_cfg_func1: codec_cfg_func1 {
|
|
pinctrl-single,pins = <
|
|
0x74 0x0 /* DMIC_CLK (IOCFG029) */
|
|
>;
|
|
pinctrl-single,bias-pulldown = <PULL_DOWN PULL_DOWN PULL_DIS PULL_DOWN>;
|
|
pinctrl-single,bias-pullup = <PULL_DIS PULL_UP PULL_DIS PULL_UP>;
|
|
pinctrl-single,drive-strength = <DRIVE1_02MA DRIVE_MASK>;
|
|
};
|
|
|
|
codec_cfg_func2: codec_cfg_func2 {
|
|
pinctrl-single,pins = <
|
|
0x78 0x0 /* CODEC_SYNC (IOCFG030) */
|
|
0x7c 0x0 /* CODEC_DI (IOCFG031) */
|
|
0x80 0x0 /* CODEC_DO (IOCFG032) */
|
|
>;
|
|
pinctrl-single,bias-pulldown = <PULL_DIS PULL_DOWN PULL_DIS PULL_DOWN>;
|
|
pinctrl-single,bias-pullup = <PULL_DIS PULL_UP PULL_DIS PULL_UP>;
|
|
pinctrl-single,drive-strength = <DRIVE1_04MA DRIVE_MASK>;
|
|
};
|
|
codec_cfg_idle2: codec_cfg_idle2 {
|
|
pinctrl-single,pins = <
|
|
0x78 0x0 /* CODEC_SYNC (IOCFG030) */
|
|
0x7c 0x0 /* CODEC_DI (IOCFG031) */
|
|
0x80 0x0 /* CODEC_DO (IOCFG032) */
|
|
>;
|
|
pinctrl-single,bias-pulldown = <PULL_DIS PULL_DOWN PULL_DIS PULL_DOWN>;
|
|
pinctrl-single,bias-pullup = <PULL_DIS PULL_UP PULL_DIS PULL_UP>;
|
|
pinctrl-single,drive-strength = <DRIVE1_02MA DRIVE_MASK>;
|
|
};
|
|
|
|
fm_cfg_func: fm_cfg_func {
|
|
pinctrl-single,pins = <
|
|
0x84 0x0 /* FM_XCLK (IOCFG033) */
|
|
0x88 0x0 /* FM_XFS (IOCFG034) */
|
|
0x8c 0x0 /* FM_DI (IOCFG035) */
|
|
0x90 0x0 /* FM_DO (IOCFG036) */
|
|
>;
|
|
pinctrl-single,bias-pulldown = <PULL_DOWN PULL_DOWN PULL_DIS PULL_DOWN>;
|
|
pinctrl-single,bias-pullup = <PULL_DIS PULL_UP PULL_DIS PULL_UP>;
|
|
pinctrl-single,drive-strength = <DRIVE1_02MA DRIVE_MASK>;
|
|
};
|
|
|
|
bt_cfg_func: bt_cfg_func {
|
|
pinctrl-single,pins = <
|
|
0x94 0x0 /* BT_XCLK (IOCFG037) */
|
|
0x98 0x0 /* BT_XFS (IOCFG038) */
|
|
0x9c 0x0 /* BT_DI (IOCFG039) */
|
|
0xa0 0x0 /* BT_DO (IOCFG040) */
|
|
>;
|
|
pinctrl-single,bias-pulldown = <PULL_DIS PULL_DOWN PULL_DIS PULL_DOWN>;
|
|
pinctrl-single,bias-pullup = <PULL_DIS PULL_UP PULL_DIS PULL_UP>;
|
|
pinctrl-single,drive-strength = <DRIVE1_02MA DRIVE_MASK>;
|
|
};
|
|
bt_cfg_idle: bt_cfg_idle {
|
|
pinctrl-single,pins = <
|
|
0x94 0x0 /* BT_XCLK (IOCFG037) */
|
|
0x98 0x0 /* BT_XFS (IOCFG038) */
|
|
0x9c 0x0 /* BT_DI (IOCFG039) */
|
|
0xa0 0x0 /* BT_DO (IOCFG040) */
|
|
>;
|
|
pinctrl-single,bias-pulldown = <PULL_DOWN PULL_DOWN PULL_DIS PULL_DOWN>;
|
|
pinctrl-single,bias-pullup = <PULL_DIS PULL_UP PULL_DIS PULL_UP>;
|
|
pinctrl-single,drive-strength = <DRIVE1_02MA DRIVE_MASK>;
|
|
};
|
|
|
|
pwm_in_cfg_func: pwm_in_cfg_func {
|
|
pinctrl-single,pins = <
|
|
0xbc 0x0 /* PWM_IN (IOCFG047) */
|
|
>;
|
|
pinctrl-single,bias-pulldown = <PULL_DOWN PULL_DOWN PULL_DIS PULL_DOWN>;
|
|
pinctrl-single,bias-pullup = <PULL_DIS PULL_UP PULL_DIS PULL_UP>;
|
|
pinctrl-single,drive-strength = <DRIVE1_02MA DRIVE_MASK>;
|
|
};
|
|
|
|
bl_pwm_cfg_func: bl_pwm_cfg_func {
|
|
pinctrl-single,pins = <
|
|
0xc0 0x0 /* BL_PWM (IOCFG048) */
|
|
>;
|
|
pinctrl-single,bias-pulldown = <PULL_DOWN PULL_DOWN PULL_DIS PULL_DOWN>;
|
|
pinctrl-single,bias-pullup = <PULL_DIS PULL_UP PULL_DIS PULL_UP>;
|
|
pinctrl-single,drive-strength = <DRIVE1_02MA DRIVE_MASK>;
|
|
};
|
|
|
|
uart0_cfg_func1: uart0_cfg_func1 {
|
|
pinctrl-single,pins = <
|
|
0xc4 0x0 /* UART0_RXD (IOCFG049) */
|
|
>;
|
|
pinctrl-single,bias-pulldown = <PULL_DIS PULL_DOWN PULL_DIS PULL_DOWN>;
|
|
pinctrl-single,bias-pullup = <PULL_UP PULL_UP PULL_DIS PULL_UP>;
|
|
pinctrl-single,drive-strength = <DRIVE1_02MA DRIVE_MASK>;
|
|
};
|
|
|
|
uart0_cfg_func2: uart0_cfg_func2 {
|
|
pinctrl-single,pins = <
|
|
0xc8 0x0 /* UART0_TXD (IOCFG050) */
|
|
>;
|
|
pinctrl-single,bias-pulldown = <PULL_DIS PULL_DOWN PULL_DIS PULL_DOWN>;
|
|
pinctrl-single,bias-pullup = <PULL_DIS PULL_UP PULL_DIS PULL_UP>;
|
|
pinctrl-single,drive-strength = <DRIVE1_04MA DRIVE_MASK>;
|
|
};
|
|
|
|
uart1_cfg_func1: uart1_cfg_func1 {
|
|
pinctrl-single,pins = <
|
|
0xcc 0x0 /* UART1_CTS_N (IOCFG051) */
|
|
0xd4 0x0 /* UART1_RXD (IOCFG053) */
|
|
>;
|
|
pinctrl-single,bias-pulldown = <PULL_DIS PULL_DOWN PULL_DIS PULL_DOWN>;
|
|
pinctrl-single,bias-pullup = <PULL_UP PULL_UP PULL_DIS PULL_UP>;
|
|
pinctrl-single,drive-strength = <DRIVE1_02MA DRIVE_MASK>;
|
|
};
|
|
|
|
uart1_cfg_func2: uart1_cfg_func2 {
|
|
pinctrl-single,pins = <
|
|
0xd0 0x0 /* UART1_RTS_N (IOCFG052) */
|
|
0xd8 0x0 /* UART1_TXD (IOCFG054) */
|
|
>;
|
|
pinctrl-single,bias-pulldown = <PULL_DIS PULL_DOWN PULL_DIS PULL_DOWN>;
|
|
pinctrl-single,bias-pullup = <PULL_DIS PULL_UP PULL_DIS PULL_UP>;
|
|
pinctrl-single,drive-strength = <DRIVE1_02MA DRIVE_MASK>;
|
|
};
|
|
|
|
uart2_cfg_func: uart2_cfg_func {
|
|
pinctrl-single,pins = <
|
|
0xdc 0x0 /* UART2_CTS_N (IOCFG055) */
|
|
0xe0 0x0 /* UART2_RTS_N (IOCFG056) */
|
|
0xe4 0x0 /* UART2_RXD (IOCFG057) */
|
|
0xe8 0x0 /* UART2_TXD (IOCFG058) */
|
|
>;
|
|
pinctrl-single,bias-pulldown = <PULL_DIS PULL_DOWN PULL_DIS PULL_DOWN>;
|
|
pinctrl-single,bias-pullup = <PULL_DIS PULL_UP PULL_DIS PULL_UP>;
|
|
pinctrl-single,drive-strength = <DRIVE1_02MA DRIVE_MASK>;
|
|
};
|
|
|
|
uart3_cfg_func: uart3_cfg_func {
|
|
pinctrl-single,pins = <
|
|
0x190 0x0 /* UART3_CTS_N (IOCFG100) */
|
|
0x194 0x0 /* UART3_RTS_N (IOCFG101) */
|
|
0x198 0x0 /* UART3_RXD (IOCFG102) */
|
|
0x19c 0x0 /* UART3_TXD (IOCFG103) */
|
|
>;
|
|
pinctrl-single,bias-pulldown = <PULL_DOWN PULL_DOWN PULL_DIS PULL_DOWN>;
|
|
pinctrl-single,bias-pullup = <PULL_DIS PULL_UP PULL_DIS PULL_UP>;
|
|
pinctrl-single,drive-strength = <DRIVE1_02MA DRIVE_MASK>;
|
|
};
|
|
|
|
uart4_cfg_func: uart4_cfg_func {
|
|
pinctrl-single,pins = <
|
|
0x1e0 0x0 /* UART4_CTS_N (IOCFG120) */
|
|
0x1e4 0x0 /* UART4_RTS_N (IOCFG121) */
|
|
0x1e8 0x0 /* UART4_RXD (IOCFG122) */
|
|
0x1ec 0x0 /* UART4_TXD (IOCFG123) */
|
|
>;
|
|
pinctrl-single,bias-pulldown = <PULL_DOWN PULL_DOWN PULL_DIS PULL_DOWN>;
|
|
pinctrl-single,bias-pullup = <PULL_DIS PULL_UP PULL_DIS PULL_UP>;
|
|
pinctrl-single,drive-strength = <DRIVE1_02MA DRIVE_MASK>;
|
|
};
|
|
|
|
uart5_cfg_func: uart5_cfg_func {
|
|
pinctrl-single,pins = <
|
|
0x1d8 0x0 /* UART4_RXD (IOCFG118) */
|
|
0x1dc 0x0 /* UART4_TXD (IOCFG119) */
|
|
>;
|
|
pinctrl-single,bias-pulldown = <PULL_DOWN PULL_DOWN PULL_DIS PULL_DOWN>;
|
|
pinctrl-single,bias-pullup = <PULL_DIS PULL_UP PULL_DIS PULL_UP>;
|
|
pinctrl-single,drive-strength = <DRIVE1_02MA DRIVE_MASK>;
|
|
};
|
|
|
|
i2c0_cfg_func: i2c0_cfg_func {
|
|
pinctrl-single,pins = <
|
|
0xec 0x0 /* I2C0_SCL (IOCFG059) */
|
|
0xf0 0x0 /* I2C0_SDA (IOCFG060) */
|
|
>;
|
|
pinctrl-single,bias-pulldown = <PULL_DIS PULL_DOWN PULL_DIS PULL_DOWN>;
|
|
pinctrl-single,bias-pullup = <PULL_DIS PULL_UP PULL_DIS PULL_UP>;
|
|
pinctrl-single,drive-strength = <DRIVE1_02MA DRIVE_MASK>;
|
|
};
|
|
|
|
i2c1_cfg_func: i2c1_cfg_func {
|
|
pinctrl-single,pins = <
|
|
0xf4 0x0 /* I2C1_SCL (IOCFG061) */
|
|
0xf8 0x0 /* I2C1_SDA (IOCFG062) */
|
|
>;
|
|
pinctrl-single,bias-pulldown = <PULL_DIS PULL_DOWN PULL_DIS PULL_DOWN>;
|
|
pinctrl-single,bias-pullup = <PULL_DIS PULL_UP PULL_DIS PULL_UP>;
|
|
pinctrl-single,drive-strength = <DRIVE1_02MA DRIVE_MASK>;
|
|
};
|
|
|
|
i2c2_cfg_func: i2c2_cfg_func {
|
|
pinctrl-single,pins = <
|
|
0xfc 0x0 /* I2C2_SCL (IOCFG063) */
|
|
0x100 0x0 /* I2C2_SDA (IOCFG064) */
|
|
>;
|
|
pinctrl-single,bias-pulldown = <PULL_DIS PULL_DOWN PULL_DIS PULL_DOWN>;
|
|
pinctrl-single,bias-pullup = <PULL_DIS PULL_UP PULL_DIS PULL_UP>;
|
|
pinctrl-single,drive-strength = <DRIVE1_02MA DRIVE_MASK>;
|
|
};
|
|
|
|
spi0_cfg_func: spi0_cfg_func {
|
|
pinctrl-single,pins = <
|
|
0x1b0 0x0 /* SPI0_DI (IOCFG108) */
|
|
0x1b4 0x0 /* SPI0_DO (IOCFG109) */
|
|
0x1b8 0x0 /* SPI0_CS_N (IOCFG110) */
|
|
0x1bc 0x0 /* SPI0_CLK (IOCFG111) */
|
|
>;
|
|
pinctrl-single,bias-pulldown = <PULL_DIS PULL_DOWN PULL_DIS PULL_DOWN>;
|
|
pinctrl-single,bias-pullup = <PULL_DIS PULL_UP PULL_DIS PULL_UP>;
|
|
pinctrl-single,drive-strength = <DRIVE1_02MA DRIVE_MASK>;
|
|
};
|
|
};
|
|
|
|
pmx2: pinmux@f8001800 {
|
|
|
|
pinctrl-names = "default";
|
|
pinctrl-0 = <
|
|
&rstout_n_cfg_func
|
|
>;
|
|
|
|
rstout_n_cfg_func: rstout_n_cfg_func {
|
|
pinctrl-single,pins = <
|
|
0x0 0x0 /* RSTOUT_N (IOCFG000) */
|
|
>;
|
|
pinctrl-single,bias-pulldown = <PULL_DIS PULL_DOWN PULL_DIS PULL_DOWN>;
|
|
pinctrl-single,bias-pullup = <PULL_DIS PULL_UP PULL_DIS PULL_UP>;
|
|
pinctrl-single,drive-strength = <DRIVE1_02MA DRIVE_MASK>;
|
|
};
|
|
|
|
pmu_peri_en_cfg_func: pmu_peri_en_cfg_func {
|
|
pinctrl-single,pins = <
|
|
0x4 0x0 /* PMU_PERI_EN (IOCFG001) */
|
|
>;
|
|
pinctrl-single,bias-pulldown = <PULL_DIS PULL_DOWN PULL_DIS PULL_DOWN>;
|
|
pinctrl-single,bias-pullup = <PULL_DIS PULL_UP PULL_DIS PULL_UP>;
|
|
pinctrl-single,drive-strength = <DRIVE1_02MA DRIVE_MASK>;
|
|
};
|
|
|
|
sysclk0_en_cfg_func: sysclk0_en_cfg_func {
|
|
pinctrl-single,pins = <
|
|
0x8 0x0 /* SYSCLK0_EN (IOCFG002) */
|
|
>;
|
|
pinctrl-single,bias-pulldown = <PULL_DIS PULL_DOWN PULL_DIS PULL_DOWN>;
|
|
pinctrl-single,bias-pullup = <PULL_DIS PULL_UP PULL_DIS PULL_UP>;
|
|
pinctrl-single,drive-strength = <DRIVE1_02MA DRIVE_MASK>;
|
|
};
|
|
|
|
jtag_tdo_cfg_func: jtag_tdo_cfg_func {
|
|
pinctrl-single,pins = <
|
|
0xc 0x0 /* JTAG_TDO (IOCFG003) */
|
|
>;
|
|
pinctrl-single,bias-pulldown = <PULL_DIS PULL_DOWN PULL_DIS PULL_DOWN>;
|
|
pinctrl-single,bias-pullup = <PULL_DIS PULL_UP PULL_DIS PULL_UP>;
|
|
pinctrl-single,drive-strength = <DRIVE1_08MA DRIVE_MASK>;
|
|
};
|
|
|
|
rf_reset_cfg_func: rf_reset_cfg_func {
|
|
pinctrl-single,pins = <
|
|
0x70 0x0 /* RF_RESET0 (IOCFG028) */
|
|
0x74 0x0 /* RF_RESET1 (IOCFG029) */
|
|
>;
|
|
pinctrl-single,bias-pulldown = <PULL_DIS PULL_DOWN PULL_DIS PULL_DOWN>;
|
|
pinctrl-single,bias-pullup = <PULL_DIS PULL_UP PULL_DIS PULL_UP>;
|
|
pinctrl-single,drive-strength = <DRIVE1_02MA DRIVE_MASK>;
|
|
};
|
|
};
|
|
};
|
|
};
|