1253 lines
30 KiB
Plaintext
1253 lines
30 KiB
Plaintext
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
|
|
/*
|
|
* Device Tree Include file for Freescale Layerscape-2080A family SoC.
|
|
*
|
|
* Copyright 2016 Freescale Semiconductor, Inc.
|
|
* Copyright 2017-2020 NXP
|
|
*
|
|
* Abhimanyu Saini <abhimanyu.saini@nxp.com>
|
|
*
|
|
*/
|
|
|
|
#include <dt-bindings/clock/fsl,qoriq-clockgen.h>
|
|
#include <dt-bindings/thermal/thermal.h>
|
|
#include <dt-bindings/interrupt-controller/arm-gic.h>
|
|
|
|
/ {
|
|
compatible = "fsl,ls2080a";
|
|
interrupt-parent = <&gic>;
|
|
#address-cells = <2>;
|
|
#size-cells = <2>;
|
|
|
|
aliases {
|
|
crypto = &crypto;
|
|
rtc1 = &ftm_alarm0;
|
|
serial0 = &serial0;
|
|
serial1 = &serial1;
|
|
serial2 = &serial2;
|
|
serial3 = &serial3;
|
|
};
|
|
|
|
cpu: cpus {
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
};
|
|
|
|
memory@80000000 {
|
|
device_type = "memory";
|
|
reg = <0x00000000 0x80000000 0 0x80000000>;
|
|
/* DRAM space - 1, size : 2 GB DRAM */
|
|
};
|
|
|
|
sysclk: sysclk {
|
|
compatible = "fixed-clock";
|
|
#clock-cells = <0>;
|
|
clock-frequency = <100000000>;
|
|
clock-output-names = "sysclk";
|
|
};
|
|
|
|
gic: interrupt-controller@6000000 {
|
|
compatible = "arm,gic-v3";
|
|
reg = <0x0 0x06000000 0 0x10000>, /* GIC Dist */
|
|
<0x0 0x06100000 0 0x100000>, /* GICR (RD_base + SGI_base) */
|
|
<0x0 0x0c0c0000 0 0x2000>, /* GICC */
|
|
<0x0 0x0c0d0000 0 0x1000>, /* GICH */
|
|
<0x0 0x0c0e0000 0 0x20000>; /* GICV */
|
|
#interrupt-cells = <3>;
|
|
#address-cells = <2>;
|
|
#size-cells = <2>;
|
|
ranges;
|
|
interrupt-controller;
|
|
interrupts = <1 9 0x4>;
|
|
|
|
its: gic-its@6020000 {
|
|
compatible = "arm,gic-v3-its";
|
|
msi-controller;
|
|
reg = <0x0 0x6020000 0 0x20000>;
|
|
};
|
|
};
|
|
|
|
rstcr: syscon@1e60000 {
|
|
compatible = "fsl,ls2080a-rstcr", "syscon";
|
|
reg = <0x0 0x1e60000 0x0 0x4>;
|
|
};
|
|
|
|
reboot {
|
|
compatible = "syscon-reboot";
|
|
regmap = <&rstcr>;
|
|
offset = <0x0>;
|
|
mask = <0x2>;
|
|
};
|
|
|
|
thermal-zones {
|
|
ddr-controller1 {
|
|
polling-delay-passive = <1000>;
|
|
polling-delay = <5000>;
|
|
thermal-sensors = <&tmu 1>;
|
|
|
|
trips {
|
|
ddr-ctrler1-crit {
|
|
temperature = <95000>;
|
|
hysteresis = <2000>;
|
|
type = "critical";
|
|
};
|
|
};
|
|
};
|
|
|
|
ddr-controller2 {
|
|
polling-delay-passive = <1000>;
|
|
polling-delay = <5000>;
|
|
thermal-sensors = <&tmu 2>;
|
|
|
|
trips {
|
|
ddr-ctrler2-crit {
|
|
temperature = <95000>;
|
|
hysteresis = <2000>;
|
|
type = "critical";
|
|
};
|
|
};
|
|
};
|
|
|
|
ddr-controller3 {
|
|
polling-delay-passive = <1000>;
|
|
polling-delay = <5000>;
|
|
thermal-sensors = <&tmu 3>;
|
|
|
|
trips {
|
|
ddr-ctrler3-crit {
|
|
temperature = <95000>;
|
|
hysteresis = <2000>;
|
|
type = "critical";
|
|
};
|
|
};
|
|
};
|
|
|
|
core-cluster1 {
|
|
polling-delay-passive = <1000>;
|
|
polling-delay = <5000>;
|
|
thermal-sensors = <&tmu 4>;
|
|
|
|
trips {
|
|
core_cluster1_alert: core-cluster1-alert {
|
|
temperature = <85000>;
|
|
hysteresis = <2000>;
|
|
type = "passive";
|
|
};
|
|
|
|
core-cluster1-crit {
|
|
temperature = <95000>;
|
|
hysteresis = <2000>;
|
|
type = "critical";
|
|
};
|
|
};
|
|
|
|
cooling-maps {
|
|
map0 {
|
|
trip = <&core_cluster1_alert>;
|
|
cooling-device =
|
|
<&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
|
|
<&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
|
|
};
|
|
};
|
|
};
|
|
|
|
core-cluster2 {
|
|
polling-delay-passive = <1000>;
|
|
polling-delay = <5000>;
|
|
thermal-sensors = <&tmu 5>;
|
|
|
|
trips {
|
|
core_cluster2_alert: core-cluster2-alert {
|
|
temperature = <85000>;
|
|
hysteresis = <2000>;
|
|
type = "passive";
|
|
};
|
|
|
|
core-cluster2-crit {
|
|
temperature = <95000>;
|
|
hysteresis = <2000>;
|
|
type = "critical";
|
|
};
|
|
};
|
|
|
|
cooling-maps {
|
|
map0 {
|
|
trip = <&core_cluster2_alert>;
|
|
cooling-device =
|
|
<&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
|
|
<&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
|
|
};
|
|
};
|
|
};
|
|
|
|
core-cluster3 {
|
|
polling-delay-passive = <1000>;
|
|
polling-delay = <5000>;
|
|
thermal-sensors = <&tmu 6>;
|
|
|
|
trips {
|
|
core_cluster3_alert: core-cluster3-alert {
|
|
temperature = <85000>;
|
|
hysteresis = <2000>;
|
|
type = "passive";
|
|
};
|
|
|
|
core-cluster3-crit {
|
|
temperature = <95000>;
|
|
hysteresis = <2000>;
|
|
type = "critical";
|
|
};
|
|
};
|
|
|
|
cooling-maps {
|
|
map0 {
|
|
trip = <&core_cluster3_alert>;
|
|
cooling-device =
|
|
<&cpu4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
|
|
<&cpu5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
|
|
};
|
|
};
|
|
};
|
|
|
|
core-cluster4 {
|
|
polling-delay-passive = <1000>;
|
|
polling-delay = <5000>;
|
|
thermal-sensors = <&tmu 7>;
|
|
|
|
trips {
|
|
core_cluster4_alert: core-cluster4-alert {
|
|
temperature = <85000>;
|
|
hysteresis = <2000>;
|
|
type = "passive";
|
|
};
|
|
|
|
core-cluster4-crit {
|
|
temperature = <95000>;
|
|
hysteresis = <2000>;
|
|
type = "critical";
|
|
};
|
|
};
|
|
|
|
cooling-maps {
|
|
map0 {
|
|
trip = <&core_cluster4_alert>;
|
|
cooling-device =
|
|
<&cpu6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
|
|
<&cpu7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
|
|
};
|
|
};
|
|
};
|
|
};
|
|
|
|
timer: timer {
|
|
compatible = "arm,armv8-timer";
|
|
interrupts = <1 13 4>, /* Physical Secure PPI, active-low */
|
|
<1 14 4>, /* Physical Non-Secure PPI, active-low */
|
|
<1 11 4>, /* Virtual PPI, active-low */
|
|
<1 10 4>; /* Hypervisor PPI, active-low */
|
|
};
|
|
|
|
pmu {
|
|
compatible = "arm,armv8-pmuv3";
|
|
interrupts = <1 7 0x8>; /* PMU PPI, Level low type */
|
|
};
|
|
|
|
psci {
|
|
compatible = "arm,psci-0.2";
|
|
method = "smc";
|
|
};
|
|
|
|
soc {
|
|
compatible = "simple-bus";
|
|
#address-cells = <2>;
|
|
#size-cells = <2>;
|
|
ranges;
|
|
dma-ranges = <0x0 0x0 0x0 0x0 0x10000 0x00000000>;
|
|
|
|
clockgen: clocking@1300000 {
|
|
compatible = "fsl,ls2080a-clockgen";
|
|
reg = <0 0x1300000 0 0xa0000>;
|
|
#clock-cells = <2>;
|
|
clocks = <&sysclk>;
|
|
};
|
|
|
|
dcfg: dcfg@1e00000 {
|
|
compatible = "fsl,ls2080a-dcfg", "syscon";
|
|
reg = <0x0 0x1e00000 0x0 0x10000>;
|
|
little-endian;
|
|
};
|
|
|
|
sfp: efuse@1e80000 {
|
|
compatible = "fsl,ls1028a-sfp";
|
|
reg = <0x0 0x1e80000 0x0 0x10000>;
|
|
clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL
|
|
QORIQ_CLK_PLL_DIV(4)>;
|
|
clock-names = "sfp";
|
|
};
|
|
|
|
isc: syscon@1f70000 {
|
|
compatible = "fsl,ls2080a-isc", "syscon";
|
|
reg = <0x0 0x1f70000 0x0 0x10000>;
|
|
little-endian;
|
|
#address-cells = <1>;
|
|
#size-cells = <1>;
|
|
ranges = <0x0 0x0 0x1f70000 0x10000>;
|
|
|
|
extirq: interrupt-controller@14 {
|
|
compatible = "fsl,ls2080a-extirq", "fsl,ls1088a-extirq";
|
|
#interrupt-cells = <2>;
|
|
#address-cells = <0>;
|
|
interrupt-controller;
|
|
reg = <0x14 4>;
|
|
interrupt-map =
|
|
<0 0 &gic GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
|
|
<1 0 &gic GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>,
|
|
<2 0 &gic GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>,
|
|
<3 0 &gic GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>,
|
|
<4 0 &gic GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>,
|
|
<5 0 &gic GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>,
|
|
<6 0 &gic GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>,
|
|
<7 0 &gic GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>,
|
|
<8 0 &gic GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>,
|
|
<9 0 &gic GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>,
|
|
<10 0 &gic GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>,
|
|
<11 0 &gic GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
|
|
interrupt-map-mask = <0xf 0x0>;
|
|
};
|
|
};
|
|
|
|
tmu: tmu@1f80000 {
|
|
compatible = "fsl,qoriq-tmu";
|
|
reg = <0x0 0x1f80000 0x0 0x10000>;
|
|
interrupts = <0 23 0x4>;
|
|
fsl,tmu-range = <0xb0000 0x9002a 0x6004c 0x30062>;
|
|
fsl,tmu-calibration = <0x00000000 0x00000026
|
|
0x00000001 0x0000002d
|
|
0x00000002 0x00000032
|
|
0x00000003 0x00000039
|
|
0x00000004 0x0000003f
|
|
0x00000005 0x00000046
|
|
0x00000006 0x0000004d
|
|
0x00000007 0x00000054
|
|
0x00000008 0x0000005a
|
|
0x00000009 0x00000061
|
|
0x0000000a 0x0000006a
|
|
0x0000000b 0x00000071
|
|
|
|
0x00010000 0x00000025
|
|
0x00010001 0x0000002c
|
|
0x00010002 0x00000035
|
|
0x00010003 0x0000003d
|
|
0x00010004 0x00000045
|
|
0x00010005 0x0000004e
|
|
0x00010006 0x00000057
|
|
0x00010007 0x00000061
|
|
0x00010008 0x0000006b
|
|
0x00010009 0x00000076
|
|
|
|
0x00020000 0x00000029
|
|
0x00020001 0x00000033
|
|
0x00020002 0x0000003d
|
|
0x00020003 0x00000049
|
|
0x00020004 0x00000056
|
|
0x00020005 0x00000061
|
|
0x00020006 0x0000006d
|
|
|
|
0x00030000 0x00000021
|
|
0x00030001 0x0000002a
|
|
0x00030002 0x0000003c
|
|
0x00030003 0x0000004e>;
|
|
little-endian;
|
|
#thermal-sensor-cells = <1>;
|
|
};
|
|
|
|
serial0: serial@21c0500 {
|
|
compatible = "fsl,ns16550", "ns16550a";
|
|
reg = <0x0 0x21c0500 0x0 0x100>;
|
|
clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL
|
|
QORIQ_CLK_PLL_DIV(4)>;
|
|
interrupts = <0 32 0x4>; /* Level high type */
|
|
};
|
|
|
|
serial1: serial@21c0600 {
|
|
compatible = "fsl,ns16550", "ns16550a";
|
|
reg = <0x0 0x21c0600 0x0 0x100>;
|
|
clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL
|
|
QORIQ_CLK_PLL_DIV(4)>;
|
|
interrupts = <0 32 0x4>; /* Level high type */
|
|
};
|
|
|
|
serial2: serial@21d0500 {
|
|
compatible = "fsl,ns16550", "ns16550a";
|
|
reg = <0x0 0x21d0500 0x0 0x100>;
|
|
clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL
|
|
QORIQ_CLK_PLL_DIV(4)>;
|
|
interrupts = <0 33 0x4>; /* Level high type */
|
|
};
|
|
|
|
serial3: serial@21d0600 {
|
|
compatible = "fsl,ns16550", "ns16550a";
|
|
reg = <0x0 0x21d0600 0x0 0x100>;
|
|
clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL
|
|
QORIQ_CLK_PLL_DIV(4)>;
|
|
interrupts = <0 33 0x4>; /* Level high type */
|
|
};
|
|
|
|
cluster1_core0_watchdog: wdt@c000000 {
|
|
compatible = "arm,sp805", "arm,primecell";
|
|
reg = <0x0 0xc000000 0x0 0x1000>;
|
|
clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL
|
|
QORIQ_CLK_PLL_DIV(4)>,
|
|
<&clockgen QORIQ_CLK_PLATFORM_PLL
|
|
QORIQ_CLK_PLL_DIV(4)>;
|
|
clock-names = "wdog_clk", "apb_pclk";
|
|
};
|
|
|
|
cluster1_core1_watchdog: wdt@c010000 {
|
|
compatible = "arm,sp805", "arm,primecell";
|
|
reg = <0x0 0xc010000 0x0 0x1000>;
|
|
clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL
|
|
QORIQ_CLK_PLL_DIV(4)>,
|
|
<&clockgen QORIQ_CLK_PLATFORM_PLL
|
|
QORIQ_CLK_PLL_DIV(4)>;
|
|
clock-names = "wdog_clk", "apb_pclk";
|
|
};
|
|
|
|
cluster2_core0_watchdog: wdt@c100000 {
|
|
compatible = "arm,sp805", "arm,primecell";
|
|
reg = <0x0 0xc100000 0x0 0x1000>;
|
|
clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL
|
|
QORIQ_CLK_PLL_DIV(4)>,
|
|
<&clockgen QORIQ_CLK_PLATFORM_PLL
|
|
QORIQ_CLK_PLL_DIV(4)>;
|
|
clock-names = "wdog_clk", "apb_pclk";
|
|
};
|
|
|
|
cluster2_core1_watchdog: wdt@c110000 {
|
|
compatible = "arm,sp805", "arm,primecell";
|
|
reg = <0x0 0xc110000 0x0 0x1000>;
|
|
clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL
|
|
QORIQ_CLK_PLL_DIV(4)>,
|
|
<&clockgen QORIQ_CLK_PLATFORM_PLL
|
|
QORIQ_CLK_PLL_DIV(4)>;
|
|
clock-names = "wdog_clk", "apb_pclk";
|
|
};
|
|
|
|
cluster3_core0_watchdog: wdt@c200000 {
|
|
compatible = "arm,sp805", "arm,primecell";
|
|
reg = <0x0 0xc200000 0x0 0x1000>;
|
|
clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL
|
|
QORIQ_CLK_PLL_DIV(4)>,
|
|
<&clockgen QORIQ_CLK_PLATFORM_PLL
|
|
QORIQ_CLK_PLL_DIV(4)>;
|
|
clock-names = "wdog_clk", "apb_pclk";
|
|
};
|
|
|
|
cluster3_core1_watchdog: wdt@c210000 {
|
|
compatible = "arm,sp805", "arm,primecell";
|
|
reg = <0x0 0xc210000 0x0 0x1000>;
|
|
clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL
|
|
QORIQ_CLK_PLL_DIV(4)>,
|
|
<&clockgen QORIQ_CLK_PLATFORM_PLL
|
|
QORIQ_CLK_PLL_DIV(4)>;
|
|
clock-names = "wdog_clk", "apb_pclk";
|
|
};
|
|
|
|
cluster4_core0_watchdog: wdt@c300000 {
|
|
compatible = "arm,sp805", "arm,primecell";
|
|
reg = <0x0 0xc300000 0x0 0x1000>;
|
|
clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL
|
|
QORIQ_CLK_PLL_DIV(4)>,
|
|
<&clockgen QORIQ_CLK_PLATFORM_PLL
|
|
QORIQ_CLK_PLL_DIV(4)>;
|
|
clock-names = "wdog_clk", "apb_pclk";
|
|
};
|
|
|
|
cluster4_core1_watchdog: wdt@c310000 {
|
|
compatible = "arm,sp805", "arm,primecell";
|
|
reg = <0x0 0xc310000 0x0 0x1000>;
|
|
clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL
|
|
QORIQ_CLK_PLL_DIV(4)>,
|
|
<&clockgen QORIQ_CLK_PLATFORM_PLL
|
|
QORIQ_CLK_PLL_DIV(4)>;
|
|
clock-names = "wdog_clk", "apb_pclk";
|
|
};
|
|
|
|
crypto: crypto@8000000 {
|
|
compatible = "fsl,sec-v5.0", "fsl,sec-v4.0";
|
|
fsl,sec-era = <8>;
|
|
#address-cells = <1>;
|
|
#size-cells = <1>;
|
|
ranges = <0x0 0x00 0x8000000 0x100000>;
|
|
reg = <0x00 0x8000000 0x0 0x100000>;
|
|
interrupts = <GIC_SPI 139 IRQ_TYPE_LEVEL_HIGH>;
|
|
dma-coherent;
|
|
|
|
sec_jr0: jr@10000 {
|
|
compatible = "fsl,sec-v5.0-job-ring",
|
|
"fsl,sec-v4.0-job-ring";
|
|
reg = <0x10000 0x10000>;
|
|
interrupts = <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>;
|
|
};
|
|
|
|
sec_jr1: jr@20000 {
|
|
compatible = "fsl,sec-v5.0-job-ring",
|
|
"fsl,sec-v4.0-job-ring";
|
|
reg = <0x20000 0x10000>;
|
|
interrupts = <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>;
|
|
};
|
|
|
|
sec_jr2: jr@30000 {
|
|
compatible = "fsl,sec-v5.0-job-ring",
|
|
"fsl,sec-v4.0-job-ring";
|
|
reg = <0x30000 0x10000>;
|
|
interrupts = <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>;
|
|
};
|
|
|
|
sec_jr3: jr@40000 {
|
|
compatible = "fsl,sec-v5.0-job-ring",
|
|
"fsl,sec-v4.0-job-ring";
|
|
reg = <0x40000 0x10000>;
|
|
interrupts = <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>;
|
|
};
|
|
};
|
|
|
|
console@8340020 {
|
|
compatible = "fsl,dpaa2-console";
|
|
reg = <0x00000000 0x08340020 0 0x2>;
|
|
};
|
|
|
|
ptp-timer@8b95000 {
|
|
compatible = "fsl,dpaa2-ptp";
|
|
reg = <0x0 0x8b95000 0x0 0x100>;
|
|
clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL
|
|
QORIQ_CLK_PLL_DIV(2)>;
|
|
little-endian;
|
|
fsl,extts-fifo;
|
|
};
|
|
|
|
emdio1: mdio@8b96000 {
|
|
compatible = "fsl,fman-memac-mdio";
|
|
reg = <0x0 0x8b96000 0x0 0x1000>;
|
|
little-endian;
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
clock-frequency = <2500000>;
|
|
clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL
|
|
QORIQ_CLK_PLL_DIV(2)>;
|
|
status = "disabled";
|
|
};
|
|
|
|
emdio2: mdio@8b97000 {
|
|
compatible = "fsl,fman-memac-mdio";
|
|
reg = <0x0 0x8b97000 0x0 0x1000>;
|
|
little-endian;
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
clock-frequency = <2500000>;
|
|
clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL
|
|
QORIQ_CLK_PLL_DIV(2)>;
|
|
status = "disabled";
|
|
};
|
|
|
|
pcs_mdio1: mdio@8c07000 {
|
|
compatible = "fsl,fman-memac-mdio";
|
|
reg = <0x0 0x8c07000 0x0 0x1000>;
|
|
little-endian;
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
status = "disabled";
|
|
|
|
pcs1: ethernet-phy@0 {
|
|
reg = <0>;
|
|
};
|
|
};
|
|
|
|
pcs_mdio2: mdio@8c0b000 {
|
|
compatible = "fsl,fman-memac-mdio";
|
|
reg = <0x0 0x8c0b000 0x0 0x1000>;
|
|
little-endian;
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
status = "disabled";
|
|
|
|
pcs2: ethernet-phy@0 {
|
|
reg = <0>;
|
|
};
|
|
};
|
|
|
|
pcs_mdio3: mdio@8c0f000 {
|
|
compatible = "fsl,fman-memac-mdio";
|
|
reg = <0x0 0x8c0f000 0x0 0x1000>;
|
|
little-endian;
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
status = "disabled";
|
|
|
|
pcs3: ethernet-phy@0 {
|
|
reg = <0>;
|
|
};
|
|
};
|
|
|
|
pcs_mdio4: mdio@8c13000 {
|
|
compatible = "fsl,fman-memac-mdio";
|
|
reg = <0x0 0x8c13000 0x0 0x1000>;
|
|
little-endian;
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
status = "disabled";
|
|
|
|
pcs4: ethernet-phy@0 {
|
|
reg = <0>;
|
|
};
|
|
};
|
|
|
|
pcs_mdio5: mdio@8c17000 {
|
|
compatible = "fsl,fman-memac-mdio";
|
|
reg = <0x0 0x8c17000 0x0 0x1000>;
|
|
little-endian;
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
status = "disabled";
|
|
|
|
pcs5: ethernet-phy@0 {
|
|
reg = <0>;
|
|
};
|
|
};
|
|
|
|
pcs_mdio6: mdio@8c1b000 {
|
|
compatible = "fsl,fman-memac-mdio";
|
|
reg = <0x0 0x8c1b000 0x0 0x1000>;
|
|
little-endian;
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
status = "disabled";
|
|
|
|
pcs6: ethernet-phy@0 {
|
|
reg = <0>;
|
|
};
|
|
};
|
|
|
|
pcs_mdio7: mdio@8c1f000 {
|
|
compatible = "fsl,fman-memac-mdio";
|
|
reg = <0x0 0x8c1f000 0x0 0x1000>;
|
|
little-endian;
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
status = "disabled";
|
|
|
|
pcs7: ethernet-phy@0 {
|
|
reg = <0>;
|
|
};
|
|
};
|
|
|
|
pcs_mdio8: mdio@8c23000 {
|
|
compatible = "fsl,fman-memac-mdio";
|
|
reg = <0x0 0x8c23000 0x0 0x1000>;
|
|
little-endian;
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
status = "disabled";
|
|
|
|
pcs8: ethernet-phy@0 {
|
|
reg = <0>;
|
|
};
|
|
};
|
|
|
|
pcs_mdio9: mdio@8c27000 {
|
|
compatible = "fsl,fman-memac-mdio";
|
|
reg = <0x0 0x8c27000 0x0 0x1000>;
|
|
little-endian;
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
status = "disabled";
|
|
|
|
pcs9: ethernet-phy@0 {
|
|
reg = <0>;
|
|
};
|
|
};
|
|
|
|
pcs_mdio10: mdio@8c2b000 {
|
|
compatible = "fsl,fman-memac-mdio";
|
|
reg = <0x0 0x8c2b000 0x0 0x1000>;
|
|
little-endian;
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
status = "disabled";
|
|
|
|
pcs10: ethernet-phy@0 {
|
|
reg = <0>;
|
|
};
|
|
};
|
|
|
|
pcs_mdio11: mdio@8c2f000 {
|
|
compatible = "fsl,fman-memac-mdio";
|
|
reg = <0x0 0x8c2f000 0x0 0x1000>;
|
|
little-endian;
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
status = "disabled";
|
|
|
|
pcs11: ethernet-phy@0 {
|
|
reg = <0>;
|
|
};
|
|
};
|
|
|
|
pcs_mdio12: mdio@8c33000 {
|
|
compatible = "fsl,fman-memac-mdio";
|
|
reg = <0x0 0x8c33000 0x0 0x1000>;
|
|
little-endian;
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
status = "disabled";
|
|
|
|
pcs12: ethernet-phy@0 {
|
|
reg = <0>;
|
|
};
|
|
};
|
|
|
|
pcs_mdio13: mdio@8c37000 {
|
|
compatible = "fsl,fman-memac-mdio";
|
|
reg = <0x0 0x8c37000 0x0 0x1000>;
|
|
little-endian;
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
status = "disabled";
|
|
|
|
pcs13: ethernet-phy@0 {
|
|
reg = <0>;
|
|
};
|
|
};
|
|
|
|
pcs_mdio14: mdio@8c3b000 {
|
|
compatible = "fsl,fman-memac-mdio";
|
|
reg = <0x0 0x8c3b000 0x0 0x1000>;
|
|
little-endian;
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
status = "disabled";
|
|
|
|
pcs14: ethernet-phy@0 {
|
|
reg = <0>;
|
|
};
|
|
};
|
|
|
|
pcs_mdio15: mdio@8c3f000 {
|
|
compatible = "fsl,fman-memac-mdio";
|
|
reg = <0x0 0x8c3f000 0x0 0x1000>;
|
|
little-endian;
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
status = "disabled";
|
|
|
|
pcs15: ethernet-phy@0 {
|
|
reg = <0>;
|
|
};
|
|
};
|
|
|
|
pcs_mdio16: mdio@8c43000 {
|
|
compatible = "fsl,fman-memac-mdio";
|
|
reg = <0x0 0x8c43000 0x0 0x1000>;
|
|
little-endian;
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
status = "disabled";
|
|
|
|
pcs16: ethernet-phy@0 {
|
|
reg = <0>;
|
|
};
|
|
};
|
|
|
|
fsl_mc: fsl-mc@80c000000 {
|
|
compatible = "fsl,qoriq-mc";
|
|
reg = <0x00000008 0x0c000000 0 0x40>, /* MC portal base */
|
|
<0x00000000 0x08340000 0 0x40000>; /* MC control reg */
|
|
msi-parent = <&its>;
|
|
iommu-map = <0 &smmu 0 0>; /* This is fixed-up by u-boot */
|
|
dma-coherent;
|
|
#address-cells = <3>;
|
|
#size-cells = <1>;
|
|
|
|
/*
|
|
* Region type 0x0 - MC portals
|
|
* Region type 0x1 - QBMAN portals
|
|
*/
|
|
ranges = <0x0 0x0 0x0 0x8 0x0c000000 0x4000000
|
|
0x1 0x0 0x0 0x8 0x18000000 0x8000000>;
|
|
|
|
/*
|
|
* Define the maximum number of MACs present on the SoC.
|
|
*/
|
|
dpmacs {
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
|
|
dpmac1: ethernet@1 {
|
|
compatible = "fsl,qoriq-mc-dpmac";
|
|
reg = <0x1>;
|
|
pcs-handle = <&pcs1>;
|
|
};
|
|
|
|
dpmac2: ethernet@2 {
|
|
compatible = "fsl,qoriq-mc-dpmac";
|
|
reg = <0x2>;
|
|
pcs-handle = <&pcs2>;
|
|
};
|
|
|
|
dpmac3: ethernet@3 {
|
|
compatible = "fsl,qoriq-mc-dpmac";
|
|
reg = <0x3>;
|
|
pcs-handle = <&pcs3>;
|
|
};
|
|
|
|
dpmac4: ethernet@4 {
|
|
compatible = "fsl,qoriq-mc-dpmac";
|
|
reg = <0x4>;
|
|
pcs-handle = <&pcs4>;
|
|
};
|
|
|
|
dpmac5: ethernet@5 {
|
|
compatible = "fsl,qoriq-mc-dpmac";
|
|
reg = <0x5>;
|
|
pcs-handle = <&pcs5>;
|
|
};
|
|
|
|
dpmac6: ethernet@6 {
|
|
compatible = "fsl,qoriq-mc-dpmac";
|
|
reg = <0x6>;
|
|
pcs-handle = <&pcs6>;
|
|
};
|
|
|
|
dpmac7: ethernet@7 {
|
|
compatible = "fsl,qoriq-mc-dpmac";
|
|
reg = <0x7>;
|
|
pcs-handle = <&pcs7>;
|
|
};
|
|
|
|
dpmac8: ethernet@8 {
|
|
compatible = "fsl,qoriq-mc-dpmac";
|
|
reg = <0x8>;
|
|
pcs-handle = <&pcs8>;
|
|
};
|
|
|
|
dpmac9: ethernet@9 {
|
|
compatible = "fsl,qoriq-mc-dpmac";
|
|
reg = <0x9>;
|
|
pcs-handle = <&pcs9>;
|
|
};
|
|
|
|
dpmac10: ethernet@a {
|
|
compatible = "fsl,qoriq-mc-dpmac";
|
|
reg = <0xa>;
|
|
pcs-handle = <&pcs10>;
|
|
};
|
|
|
|
dpmac11: ethernet@b {
|
|
compatible = "fsl,qoriq-mc-dpmac";
|
|
reg = <0xb>;
|
|
pcs-handle = <&pcs11>;
|
|
};
|
|
|
|
dpmac12: ethernet@c {
|
|
compatible = "fsl,qoriq-mc-dpmac";
|
|
reg = <0xc>;
|
|
pcs-handle = <&pcs12>;
|
|
};
|
|
|
|
dpmac13: ethernet@d {
|
|
compatible = "fsl,qoriq-mc-dpmac";
|
|
reg = <0xd>;
|
|
pcs-handle = <&pcs13>;
|
|
};
|
|
|
|
dpmac14: ethernet@e {
|
|
compatible = "fsl,qoriq-mc-dpmac";
|
|
reg = <0xe>;
|
|
pcs-handle = <&pcs14>;
|
|
};
|
|
|
|
dpmac15: ethernet@f {
|
|
compatible = "fsl,qoriq-mc-dpmac";
|
|
reg = <0xf>;
|
|
pcs-handle = <&pcs15>;
|
|
};
|
|
|
|
dpmac16: ethernet@10 {
|
|
compatible = "fsl,qoriq-mc-dpmac";
|
|
reg = <0x10>;
|
|
pcs-handle = <&pcs16>;
|
|
};
|
|
};
|
|
};
|
|
|
|
smmu: iommu@5000000 {
|
|
compatible = "arm,mmu-500";
|
|
reg = <0 0x5000000 0 0x800000>;
|
|
#global-interrupts = <12>;
|
|
#iommu-cells = <1>;
|
|
stream-match-mask = <0x7C00>;
|
|
dma-coherent;
|
|
interrupts = <0 13 4>, /* global secure fault */
|
|
<0 14 4>, /* combined secure interrupt */
|
|
<0 15 4>, /* global non-secure fault */
|
|
<0 16 4>, /* combined non-secure interrupt */
|
|
/* performance counter interrupts 0-7 */
|
|
<0 211 4>, <0 212 4>,
|
|
<0 213 4>, <0 214 4>,
|
|
<0 215 4>, <0 216 4>,
|
|
<0 217 4>, <0 218 4>,
|
|
/* per context interrupt, 64 interrupts */
|
|
<0 146 4>, <0 147 4>,
|
|
<0 148 4>, <0 149 4>,
|
|
<0 150 4>, <0 151 4>,
|
|
<0 152 4>, <0 153 4>,
|
|
<0 154 4>, <0 155 4>,
|
|
<0 156 4>, <0 157 4>,
|
|
<0 158 4>, <0 159 4>,
|
|
<0 160 4>, <0 161 4>,
|
|
<0 162 4>, <0 163 4>,
|
|
<0 164 4>, <0 165 4>,
|
|
<0 166 4>, <0 167 4>,
|
|
<0 168 4>, <0 169 4>,
|
|
<0 170 4>, <0 171 4>,
|
|
<0 172 4>, <0 173 4>,
|
|
<0 174 4>, <0 175 4>,
|
|
<0 176 4>, <0 177 4>,
|
|
<0 178 4>, <0 179 4>,
|
|
<0 180 4>, <0 181 4>,
|
|
<0 182 4>, <0 183 4>,
|
|
<0 184 4>, <0 185 4>,
|
|
<0 186 4>, <0 187 4>,
|
|
<0 188 4>, <0 189 4>,
|
|
<0 190 4>, <0 191 4>,
|
|
<0 192 4>, <0 193 4>,
|
|
<0 194 4>, <0 195 4>,
|
|
<0 196 4>, <0 197 4>,
|
|
<0 198 4>, <0 199 4>,
|
|
<0 200 4>, <0 201 4>,
|
|
<0 202 4>, <0 203 4>,
|
|
<0 204 4>, <0 205 4>,
|
|
<0 206 4>, <0 207 4>,
|
|
<0 208 4>, <0 209 4>;
|
|
};
|
|
|
|
dspi: spi@2100000 {
|
|
status = "disabled";
|
|
compatible = "fsl,ls2080a-dspi", "fsl,ls2085a-dspi";
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
reg = <0x0 0x2100000 0x0 0x10000>;
|
|
interrupts = <0 26 0x4>; /* Level high type */
|
|
clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL
|
|
QORIQ_CLK_PLL_DIV(4)>;
|
|
clock-names = "dspi";
|
|
spi-num-chipselects = <5>;
|
|
};
|
|
|
|
esdhc: esdhc@2140000 {
|
|
status = "disabled";
|
|
compatible = "fsl,ls2080a-esdhc", "fsl,esdhc";
|
|
reg = <0x0 0x2140000 0x0 0x10000>;
|
|
interrupts = <0 28 0x4>; /* Level high type */
|
|
clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL
|
|
QORIQ_CLK_PLL_DIV(2)>;
|
|
voltage-ranges = <1800 1800 3300 3300>;
|
|
sdhci,auto-cmd12;
|
|
little-endian;
|
|
bus-width = <4>;
|
|
};
|
|
|
|
gpio0: gpio@2300000 {
|
|
compatible = "fsl,ls2080a-gpio", "fsl,qoriq-gpio";
|
|
reg = <0x0 0x2300000 0x0 0x10000>;
|
|
interrupts = <0 36 0x4>; /* Level high type */
|
|
gpio-controller;
|
|
little-endian;
|
|
#gpio-cells = <2>;
|
|
interrupt-controller;
|
|
#interrupt-cells = <2>;
|
|
};
|
|
|
|
gpio1: gpio@2310000 {
|
|
compatible = "fsl,ls2080a-gpio", "fsl,qoriq-gpio";
|
|
reg = <0x0 0x2310000 0x0 0x10000>;
|
|
interrupts = <0 36 0x4>; /* Level high type */
|
|
gpio-controller;
|
|
little-endian;
|
|
#gpio-cells = <2>;
|
|
interrupt-controller;
|
|
#interrupt-cells = <2>;
|
|
};
|
|
|
|
gpio2: gpio@2320000 {
|
|
compatible = "fsl,ls2080a-gpio", "fsl,qoriq-gpio";
|
|
reg = <0x0 0x2320000 0x0 0x10000>;
|
|
interrupts = <0 37 0x4>; /* Level high type */
|
|
gpio-controller;
|
|
little-endian;
|
|
#gpio-cells = <2>;
|
|
interrupt-controller;
|
|
#interrupt-cells = <2>;
|
|
};
|
|
|
|
gpio3: gpio@2330000 {
|
|
compatible = "fsl,ls2080a-gpio", "fsl,qoriq-gpio";
|
|
reg = <0x0 0x2330000 0x0 0x10000>;
|
|
interrupts = <0 37 0x4>; /* Level high type */
|
|
gpio-controller;
|
|
little-endian;
|
|
#gpio-cells = <2>;
|
|
interrupt-controller;
|
|
#interrupt-cells = <2>;
|
|
};
|
|
|
|
i2c0: i2c@2000000 {
|
|
status = "disabled";
|
|
compatible = "fsl,vf610-i2c";
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
reg = <0x0 0x2000000 0x0 0x10000>;
|
|
interrupts = <0 34 0x4>; /* Level high type */
|
|
clock-names = "i2c";
|
|
clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL
|
|
QORIQ_CLK_PLL_DIV(4)>;
|
|
};
|
|
|
|
i2c1: i2c@2010000 {
|
|
status = "disabled";
|
|
compatible = "fsl,vf610-i2c";
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
reg = <0x0 0x2010000 0x0 0x10000>;
|
|
interrupts = <0 34 0x4>; /* Level high type */
|
|
clock-names = "i2c";
|
|
clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL
|
|
QORIQ_CLK_PLL_DIV(4)>;
|
|
};
|
|
|
|
i2c2: i2c@2020000 {
|
|
status = "disabled";
|
|
compatible = "fsl,vf610-i2c";
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
reg = <0x0 0x2020000 0x0 0x10000>;
|
|
interrupts = <0 35 0x4>; /* Level high type */
|
|
clock-names = "i2c";
|
|
clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL
|
|
QORIQ_CLK_PLL_DIV(4)>;
|
|
};
|
|
|
|
i2c3: i2c@2030000 {
|
|
status = "disabled";
|
|
compatible = "fsl,vf610-i2c";
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
reg = <0x0 0x2030000 0x0 0x10000>;
|
|
interrupts = <0 35 0x4>; /* Level high type */
|
|
clock-names = "i2c";
|
|
clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL
|
|
QORIQ_CLK_PLL_DIV(4)>;
|
|
};
|
|
|
|
ifc: memory-controller@2240000 {
|
|
compatible = "fsl,ifc";
|
|
reg = <0x0 0x2240000 0x0 0x20000>;
|
|
interrupts = <0 21 0x4>; /* Level high type */
|
|
little-endian;
|
|
#address-cells = <2>;
|
|
#size-cells = <1>;
|
|
|
|
ranges = <0 0 0x5 0x80000000 0x08000000
|
|
2 0 0x5 0x30000000 0x00010000
|
|
3 0 0x5 0x20000000 0x00010000>;
|
|
};
|
|
|
|
qspi: spi@20c0000 {
|
|
compatible = "fsl,ls2080a-qspi";
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
reg = <0x0 0x20c0000 0x0 0x10000>,
|
|
<0x0 0x20000000 0x0 0x10000000>;
|
|
reg-names = "QuadSPI", "QuadSPI-memory";
|
|
interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>;
|
|
clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL
|
|
QORIQ_CLK_PLL_DIV(4)>,
|
|
<&clockgen QORIQ_CLK_PLATFORM_PLL
|
|
QORIQ_CLK_PLL_DIV(4)>;
|
|
clock-names = "qspi_en", "qspi";
|
|
status = "disabled";
|
|
};
|
|
|
|
pcie1: pcie@3400000 {
|
|
compatible = "fsl,ls2080a-pcie", "fsl,ls2085a-pcie";
|
|
reg-names = "regs", "config";
|
|
interrupts = <0 108 0x4>; /* Level high type */
|
|
interrupt-names = "intr";
|
|
#address-cells = <3>;
|
|
#size-cells = <2>;
|
|
device_type = "pci";
|
|
dma-coherent;
|
|
num-viewport = <6>;
|
|
bus-range = <0x0 0xff>;
|
|
msi-parent = <&its>;
|
|
#interrupt-cells = <1>;
|
|
interrupt-map-mask = <0 0 0 7>;
|
|
interrupt-map = <0000 0 0 1 &gic 0 0 0 109 4>,
|
|
<0000 0 0 2 &gic 0 0 0 110 4>,
|
|
<0000 0 0 3 &gic 0 0 0 111 4>,
|
|
<0000 0 0 4 &gic 0 0 0 112 4>;
|
|
iommu-map = <0 &smmu 0 1>; /* Fixed-up by bootloader */
|
|
status = "disabled";
|
|
};
|
|
|
|
pcie2: pcie@3500000 {
|
|
compatible = "fsl,ls2080a-pcie", "fsl,ls2085a-pcie";
|
|
reg-names = "regs", "config";
|
|
interrupts = <0 113 0x4>; /* Level high type */
|
|
interrupt-names = "intr";
|
|
#address-cells = <3>;
|
|
#size-cells = <2>;
|
|
device_type = "pci";
|
|
dma-coherent;
|
|
num-viewport = <6>;
|
|
bus-range = <0x0 0xff>;
|
|
msi-parent = <&its>;
|
|
#interrupt-cells = <1>;
|
|
interrupt-map-mask = <0 0 0 7>;
|
|
interrupt-map = <0000 0 0 1 &gic 0 0 0 114 4>,
|
|
<0000 0 0 2 &gic 0 0 0 115 4>,
|
|
<0000 0 0 3 &gic 0 0 0 116 4>,
|
|
<0000 0 0 4 &gic 0 0 0 117 4>;
|
|
iommu-map = <0 &smmu 0 1>; /* Fixed-up by bootloader */
|
|
status = "disabled";
|
|
};
|
|
|
|
pcie3: pcie@3600000 {
|
|
compatible = "fsl,ls2080a-pcie", "fsl,ls2085a-pcie";
|
|
reg-names = "regs", "config";
|
|
interrupts = <0 118 0x4>; /* Level high type */
|
|
interrupt-names = "intr";
|
|
#address-cells = <3>;
|
|
#size-cells = <2>;
|
|
device_type = "pci";
|
|
dma-coherent;
|
|
num-viewport = <256>;
|
|
bus-range = <0x0 0xff>;
|
|
msi-parent = <&its>;
|
|
#interrupt-cells = <1>;
|
|
interrupt-map-mask = <0 0 0 7>;
|
|
interrupt-map = <0000 0 0 1 &gic 0 0 0 119 4>,
|
|
<0000 0 0 2 &gic 0 0 0 120 4>,
|
|
<0000 0 0 3 &gic 0 0 0 121 4>,
|
|
<0000 0 0 4 &gic 0 0 0 122 4>;
|
|
iommu-map = <0 &smmu 0 1>; /* Fixed-up by bootloader */
|
|
status = "disabled";
|
|
};
|
|
|
|
pcie4: pcie@3700000 {
|
|
compatible = "fsl,ls2080a-pcie", "fsl,ls2085a-pcie";
|
|
reg-names = "regs", "config";
|
|
interrupts = <0 123 0x4>; /* Level high type */
|
|
interrupt-names = "intr";
|
|
#address-cells = <3>;
|
|
#size-cells = <2>;
|
|
device_type = "pci";
|
|
dma-coherent;
|
|
num-viewport = <6>;
|
|
bus-range = <0x0 0xff>;
|
|
msi-parent = <&its>;
|
|
#interrupt-cells = <1>;
|
|
interrupt-map-mask = <0 0 0 7>;
|
|
interrupt-map = <0000 0 0 1 &gic 0 0 0 124 4>,
|
|
<0000 0 0 2 &gic 0 0 0 125 4>,
|
|
<0000 0 0 3 &gic 0 0 0 126 4>,
|
|
<0000 0 0 4 &gic 0 0 0 127 4>;
|
|
iommu-map = <0 &smmu 0 1>; /* Fixed-up by bootloader */
|
|
status = "disabled";
|
|
};
|
|
|
|
sata0: sata@3200000 {
|
|
status = "disabled";
|
|
compatible = "fsl,ls2080a-ahci";
|
|
reg = <0x0 0x3200000 0x0 0x10000>;
|
|
interrupts = <0 133 0x4>; /* Level high type */
|
|
clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL
|
|
QORIQ_CLK_PLL_DIV(4)>;
|
|
dma-coherent;
|
|
};
|
|
|
|
sata1: sata@3210000 {
|
|
status = "disabled";
|
|
compatible = "fsl,ls2080a-ahci";
|
|
reg = <0x0 0x3210000 0x0 0x10000>;
|
|
interrupts = <0 136 0x4>; /* Level high type */
|
|
clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL
|
|
QORIQ_CLK_PLL_DIV(4)>;
|
|
dma-coherent;
|
|
};
|
|
|
|
usb0: usb@3100000 {
|
|
status = "disabled";
|
|
compatible = "snps,dwc3";
|
|
reg = <0x0 0x3100000 0x0 0x10000>;
|
|
interrupts = <0 80 0x4>; /* Level high type */
|
|
dr_mode = "host";
|
|
snps,quirk-frame-length-adjustment = <0x20>;
|
|
snps,dis_rxdet_inp3_quirk;
|
|
snps,incr-burst-type-adjustment = <1>, <4>, <8>, <16>;
|
|
};
|
|
|
|
usb1: usb@3110000 {
|
|
status = "disabled";
|
|
compatible = "snps,dwc3";
|
|
reg = <0x0 0x3110000 0x0 0x10000>;
|
|
interrupts = <0 81 0x4>; /* Level high type */
|
|
dr_mode = "host";
|
|
snps,quirk-frame-length-adjustment = <0x20>;
|
|
snps,dis_rxdet_inp3_quirk;
|
|
snps,incr-burst-type-adjustment = <1>, <4>, <8>, <16>;
|
|
};
|
|
|
|
ccn@4000000 {
|
|
compatible = "arm,ccn-504";
|
|
reg = <0x0 0x04000000 0x0 0x01000000>;
|
|
interrupts = <0 12 4>;
|
|
};
|
|
|
|
rcpm: power-controller@1e34040 {
|
|
compatible = "fsl,ls208xa-rcpm", "fsl,qoriq-rcpm-2.1+";
|
|
reg = <0x0 0x1e34040 0x0 0x18>;
|
|
#fsl,rcpm-wakeup-cells = <6>;
|
|
little-endian;
|
|
};
|
|
|
|
ftm_alarm0: timer@2800000 {
|
|
compatible = "fsl,ls208xa-ftm-alarm";
|
|
reg = <0x0 0x2800000 0x0 0x10000>;
|
|
fsl,rcpm-wakeup = <&rcpm 0x0 0x0 0x0 0x0 0x4000 0x0>;
|
|
interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>;
|
|
};
|
|
};
|
|
|
|
ddr1: memory-controller@1080000 {
|
|
compatible = "fsl,qoriq-memory-controller";
|
|
reg = <0x0 0x1080000 0x0 0x1000>;
|
|
interrupts = <0 17 0x4>;
|
|
little-endian;
|
|
};
|
|
|
|
ddr2: memory-controller@1090000 {
|
|
compatible = "fsl,qoriq-memory-controller";
|
|
reg = <0x0 0x1090000 0x0 0x1000>;
|
|
interrupts = <0 18 0x4>;
|
|
little-endian;
|
|
};
|
|
|
|
firmware {
|
|
optee {
|
|
compatible = "linaro,optee-tz";
|
|
method = "smc";
|
|
};
|
|
};
|
|
};
|