164 lines
2.5 KiB
Plaintext
164 lines
2.5 KiB
Plaintext
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
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/*
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* Device Tree Include file for Freescale Layerscape-1046A family SoC.
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*
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* Copyright 2019 NXP.
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*
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*/
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/dts-v1/;
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#include "fsl-ls1046a.dtsi"
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/ {
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model = "LS1046A FRWY Board";
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compatible = "fsl,ls1046a-frwy", "fsl,ls1046a";
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aliases {
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serial0 = &duart0;
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serial1 = &duart1;
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serial2 = &duart2;
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serial3 = &duart3;
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};
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chosen {
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stdout-path = "serial0:115200n8";
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};
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sb_3v3: regulator-sb3v3 {
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compatible = "regulator-fixed";
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regulator-name = "LT8642SEV-3.3V";
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regulator-min-microvolt = <3300000>;
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regulator-max-microvolt = <3300000>;
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regulator-boot-on;
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regulator-always-on;
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};
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};
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&duart0 {
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status = "okay";
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};
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&duart1 {
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status = "okay";
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};
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&duart2 {
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status = "okay";
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};
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&duart3 {
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status = "okay";
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};
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&i2c0 {
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status = "okay";
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i2c-mux@77 {
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compatible = "nxp,pca9546";
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reg = <0x77>;
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#address-cells = <1>;
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#size-cells = <0>;
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i2c@0 {
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#address-cells = <1>;
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#size-cells = <0>;
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reg = <0>;
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power-monitor@40 {
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compatible = "ti,ina220";
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reg = <0x40>;
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shunt-resistor = <1000>;
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};
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temperature-sensor@4c {
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compatible = "nxp,sa56004";
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reg = <0x4c>;
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vcc-supply = <&sb_3v3>;
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};
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rtc@51 {
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compatible = "nxp,pcf2129";
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reg = <0x51>;
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};
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eeprom@52 {
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compatible = "onnn,cat24c04", "atmel,24c04";
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reg = <0x52>;
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};
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};
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};
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};
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&ifc {
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#address-cells = <2>;
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#size-cells = <1>;
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/* NAND Flash */
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ranges = <0x0 0x0 0x0 0x7e800000 0x00010000>;
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status = "okay";
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nand@0,0 {
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compatible = "fsl,ifc-nand";
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#address-cells = <1>;
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#size-cells = <1>;
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reg = <0x0 0x0 0x10000>;
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};
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};
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&qspi {
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status = "okay";
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mt25qu512a0: flash@0 {
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compatible = "jedec,spi-nor";
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#address-cells = <1>;
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#size-cells = <1>;
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spi-max-frequency = <50000000>;
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spi-rx-bus-width = <4>;
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spi-tx-bus-width = <1>;
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reg = <0>;
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};
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};
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#include "fsl-ls1046-post.dtsi"
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&fman0 {
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ethernet@e0000 {
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phy-handle = <&qsgmii_phy4>;
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phy-connection-type = "qsgmii";
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};
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ethernet@e8000 {
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phy-handle = <&qsgmii_phy2>;
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phy-connection-type = "qsgmii";
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};
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ethernet@ea000 {
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phy-handle = <&qsgmii_phy1>;
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phy-connection-type = "qsgmii";
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};
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ethernet@f2000 {
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phy-handle = <&qsgmii_phy3>;
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phy-connection-type = "qsgmii";
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};
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mdio@fd000 {
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qsgmii_phy1: ethernet-phy@1c {
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reg = <0x1c>;
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};
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qsgmii_phy2: ethernet-phy@1d {
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reg = <0x1d>;
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};
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qsgmii_phy3: ethernet-phy@1e {
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reg = <0x1e>;
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};
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qsgmii_phy4: ethernet-phy@1f {
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reg = <0x1f>;
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};
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};
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};
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