183 lines
5.1 KiB
Plaintext
183 lines
5.1 KiB
Plaintext
// SPDX-License-Identifier: GPL-2.0
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/*
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* ARM Ltd. Fast Models
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*
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* Architecture Envelope Model (AEM) ARMv8-A
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* ARMAEMv8AMPCT
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*
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* RTSM_VE_AEMv8A.lisa
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*/
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/dts-v1/;
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#include <dt-bindings/interrupt-controller/arm-gic.h>
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/memreserve/ 0x80000000 0x00010000;
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#include "rtsm_ve-motherboard.dtsi"
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/ {
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model = "RTSM_VE_AEMv8A";
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compatible = "arm,rtsm_ve,aemv8a", "arm,vexpress";
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interrupt-parent = <&gic>;
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#address-cells = <2>;
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#size-cells = <2>;
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chosen { };
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aliases {
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serial0 = &v2m_serial0;
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serial1 = &v2m_serial1;
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serial2 = &v2m_serial2;
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serial3 = &v2m_serial3;
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};
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cpus {
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#address-cells = <2>;
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#size-cells = <0>;
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cpu@0 {
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device_type = "cpu";
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compatible = "arm,armv8";
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reg = <0x0 0x0>;
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enable-method = "spin-table";
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cpu-release-addr = <0x0 0x8000fff8>;
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next-level-cache = <&L2_0>;
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};
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cpu@1 {
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device_type = "cpu";
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compatible = "arm,armv8";
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reg = <0x0 0x1>;
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enable-method = "spin-table";
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cpu-release-addr = <0x0 0x8000fff8>;
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next-level-cache = <&L2_0>;
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};
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cpu@2 {
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device_type = "cpu";
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compatible = "arm,armv8";
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reg = <0x0 0x2>;
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enable-method = "spin-table";
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cpu-release-addr = <0x0 0x8000fff8>;
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next-level-cache = <&L2_0>;
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};
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cpu@3 {
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device_type = "cpu";
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compatible = "arm,armv8";
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reg = <0x0 0x3>;
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enable-method = "spin-table";
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cpu-release-addr = <0x0 0x8000fff8>;
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next-level-cache = <&L2_0>;
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};
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L2_0: l2-cache0 {
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compatible = "cache";
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};
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};
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memory@80000000 {
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device_type = "memory";
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reg = <0x00000000 0x80000000 0 0x80000000>,
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<0x00000008 0x80000000 0 0x80000000>;
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};
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reserved-memory {
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#address-cells = <2>;
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#size-cells = <2>;
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ranges;
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/* Chipselect 2,00000000 is physically at 0x18000000 */
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vram: vram@18000000 {
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/* 8 MB of designated video RAM */
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compatible = "shared-dma-pool";
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reg = <0x00000000 0x18000000 0 0x00800000>;
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no-map;
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};
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};
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gic: interrupt-controller@2c001000 {
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compatible = "arm,gic-400", "arm,cortex-a15-gic";
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#interrupt-cells = <3>;
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#address-cells = <0>;
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interrupt-controller;
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reg = <0x0 0x2c001000 0 0x1000>,
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<0x0 0x2c002000 0 0x2000>,
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<0x0 0x2c004000 0 0x2000>,
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<0x0 0x2c006000 0 0x2000>;
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interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
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};
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timer {
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compatible = "arm,armv8-timer";
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interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
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<GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
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<GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
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<GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>;
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clock-frequency = <100000000>;
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};
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pmu {
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compatible = "arm,armv8-pmuv3";
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interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>;
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};
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panel {
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compatible = "arm,rtsm-display";
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port {
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panel_in: endpoint {
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remote-endpoint = <&clcd_pads>;
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};
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};
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};
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bus@8000000 {
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#interrupt-cells = <1>;
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interrupt-map-mask = <0 0 63>;
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interrupt-map = <0 0 0 &gic GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
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<0 0 1 &gic GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>,
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<0 0 2 &gic GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>,
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<0 0 3 &gic GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>,
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<0 0 4 &gic GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>,
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<0 0 5 &gic GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>,
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<0 0 6 &gic GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>,
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<0 0 7 &gic GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>,
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<0 0 8 &gic GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>,
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<0 0 9 &gic GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>,
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<0 0 10 &gic GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>,
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<0 0 11 &gic GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>,
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<0 0 12 &gic GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>,
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<0 0 13 &gic GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>,
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<0 0 14 &gic GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>,
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<0 0 15 &gic GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>,
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<0 0 16 &gic GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>,
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<0 0 17 &gic GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>,
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<0 0 18 &gic GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>,
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<0 0 19 &gic GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>,
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<0 0 20 &gic GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>,
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<0 0 21 &gic GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>,
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<0 0 22 &gic GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>,
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<0 0 23 &gic GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>,
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<0 0 24 &gic GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>,
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<0 0 25 &gic GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>,
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<0 0 26 &gic GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>,
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<0 0 27 &gic GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>,
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<0 0 28 &gic GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>,
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<0 0 29 &gic GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>,
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<0 0 30 &gic GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>,
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<0 0 31 &gic GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>,
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<0 0 32 &gic GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>,
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<0 0 33 &gic GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>,
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<0 0 34 &gic GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>,
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<0 0 35 &gic GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>,
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<0 0 36 &gic GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>,
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<0 0 37 &gic GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>,
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<0 0 38 &gic GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>,
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<0 0 39 &gic GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>,
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<0 0 40 &gic GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>,
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<0 0 41 &gic GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>,
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<0 0 42 &gic GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>;
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};
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};
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