171 lines
4.0 KiB
C
171 lines
4.0 KiB
C
// SPDX-License-Identifier: GPL-2.0+
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//
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// Copyright (c) 2006 Simtec Electronics
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// Ben Dooks <ben@simtec.co.uk>
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//
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// S3C2410 (and compatible) Power Manager (Suspend-To-RAM) support
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#include <linux/init.h>
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#include <linux/suspend.h>
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#include <linux/errno.h>
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#include <linux/time.h>
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#include <linux/device.h>
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#include <linux/syscore_ops.h>
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#include <linux/gpio.h>
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#include <linux/io.h>
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#include <asm/mach-types.h>
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#include "regs-gpio.h"
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#include "gpio-samsung.h"
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#include "gpio-cfg.h"
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#include "cpu.h"
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#include "pm.h"
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#include "h1940.h"
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static void s3c2410_pm_prepare(void)
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{
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/* ensure at least GSTATUS3 has the resume address */
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__raw_writel(__pa_symbol(s3c_cpu_resume), S3C2410_GSTATUS3);
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S3C_PMDBG("GSTATUS3 0x%08x\n", __raw_readl(S3C2410_GSTATUS3));
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S3C_PMDBG("GSTATUS4 0x%08x\n", __raw_readl(S3C2410_GSTATUS4));
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if (machine_is_h1940()) {
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void *base = phys_to_virt(H1940_SUSPEND_CHECK);
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unsigned long ptr;
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unsigned long calc = 0;
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/* generate check for the bootloader to check on resume */
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for (ptr = 0; ptr < 0x40000; ptr += 0x400)
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calc += __raw_readl(base+ptr);
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__raw_writel(calc, phys_to_virt(H1940_SUSPEND_CHECKSUM));
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}
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/* RX3715 and RX1950 use similar to H1940 code and the
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* same offsets for resume and checksum pointers */
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if (machine_is_rx3715() || machine_is_rx1950()) {
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void *base = phys_to_virt(H1940_SUSPEND_CHECK);
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unsigned long ptr;
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unsigned long calc = 0;
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/* generate check for the bootloader to check on resume */
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for (ptr = 0; ptr < 0x40000; ptr += 0x4)
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calc += __raw_readl(base+ptr);
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__raw_writel(calc, phys_to_virt(H1940_SUSPEND_CHECKSUM));
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}
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if (machine_is_aml_m5900()) {
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gpio_request_one(S3C2410_GPF(2), GPIOF_OUT_INIT_HIGH, NULL);
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gpio_free(S3C2410_GPF(2));
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}
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if (machine_is_rx1950()) {
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/* According to S3C2442 user's manual, page 7-17,
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* when the system is operating in NAND boot mode,
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* the hardware pin configuration - EINT[23:21] –
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* must be set as input for starting up after
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* wakeup from sleep mode
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*/
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s3c_gpio_cfgpin(S3C2410_GPG(13), S3C2410_GPIO_INPUT);
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s3c_gpio_cfgpin(S3C2410_GPG(14), S3C2410_GPIO_INPUT);
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s3c_gpio_cfgpin(S3C2410_GPG(15), S3C2410_GPIO_INPUT);
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}
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}
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static void s3c2410_pm_resume(void)
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{
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unsigned long tmp;
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/* unset the return-from-sleep flag, to ensure reset */
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tmp = __raw_readl(S3C2410_GSTATUS2);
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tmp &= S3C2410_GSTATUS2_OFFRESET;
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__raw_writel(tmp, S3C2410_GSTATUS2);
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if (machine_is_aml_m5900()) {
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gpio_request_one(S3C2410_GPF(2), GPIOF_OUT_INIT_LOW, NULL);
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gpio_free(S3C2410_GPF(2));
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}
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}
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struct syscore_ops s3c2410_pm_syscore_ops = {
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.resume = s3c2410_pm_resume,
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};
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static int s3c2410_pm_add(struct device *dev, struct subsys_interface *sif)
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{
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pm_cpu_prep = s3c2410_pm_prepare;
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pm_cpu_sleep = s3c2410_cpu_suspend;
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return 0;
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}
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#if defined(CONFIG_CPU_S3C2410)
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static struct subsys_interface s3c2410_pm_interface = {
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.name = "s3c2410_pm",
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.subsys = &s3c2410_subsys,
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.add_dev = s3c2410_pm_add,
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};
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/* register ourselves */
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static int __init s3c2410_pm_drvinit(void)
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{
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return subsys_interface_register(&s3c2410_pm_interface);
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}
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arch_initcall(s3c2410_pm_drvinit);
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static struct subsys_interface s3c2410a_pm_interface = {
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.name = "s3c2410a_pm",
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.subsys = &s3c2410a_subsys,
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.add_dev = s3c2410_pm_add,
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};
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static int __init s3c2410a_pm_drvinit(void)
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{
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return subsys_interface_register(&s3c2410a_pm_interface);
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}
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arch_initcall(s3c2410a_pm_drvinit);
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#endif
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#if defined(CONFIG_CPU_S3C2440)
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static struct subsys_interface s3c2440_pm_interface = {
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.name = "s3c2440_pm",
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.subsys = &s3c2440_subsys,
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.add_dev = s3c2410_pm_add,
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};
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static int __init s3c2440_pm_drvinit(void)
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{
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return subsys_interface_register(&s3c2440_pm_interface);
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}
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arch_initcall(s3c2440_pm_drvinit);
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#endif
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#if defined(CONFIG_CPU_S3C2442)
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static struct subsys_interface s3c2442_pm_interface = {
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.name = "s3c2442_pm",
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.subsys = &s3c2442_subsys,
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.add_dev = s3c2410_pm_add,
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};
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static int __init s3c2442_pm_drvinit(void)
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{
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return subsys_interface_register(&s3c2442_pm_interface);
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}
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arch_initcall(s3c2442_pm_drvinit);
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#endif
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