230 lines
6.0 KiB
C
230 lines
6.0 KiB
C
// SPDX-License-Identifier: GPL-2.0-only
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/*
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* OMAP2xxx PRM module functions
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*
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* Copyright (C) 2010-2012 Texas Instruments, Inc.
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* Copyright (C) 2010 Nokia Corporation
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* Benoît Cousson
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* Paul Walmsley
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* Rajendra Nayak <rnayak@ti.com>
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*/
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#include <linux/kernel.h>
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#include <linux/errno.h>
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#include <linux/err.h>
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#include <linux/io.h>
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#include <linux/irq.h>
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#include "powerdomain.h"
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#include "clockdomain.h"
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#include "prm2xxx.h"
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#include "cm2xxx_3xxx.h"
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#include "prm-regbits-24xx.h"
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/*
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* OMAP24xx PM_PWSTCTRL_*.POWERSTATE and PM_PWSTST_*.LASTSTATEENTERED bits -
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* these are reversed from the bits used on OMAP3+
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*/
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#define OMAP24XX_PWRDM_POWER_ON 0x0
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#define OMAP24XX_PWRDM_POWER_RET 0x1
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#define OMAP24XX_PWRDM_POWER_OFF 0x3
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/*
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* omap2xxx_prm_reset_src_map - map from bits in the PRM_RSTST_WKUP
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* hardware register (which are specific to the OMAP2xxx SoCs) to
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* reset source ID bit shifts (which is an OMAP SoC-independent
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* enumeration)
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*/
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static struct prm_reset_src_map omap2xxx_prm_reset_src_map[] = {
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{ OMAP_GLOBALCOLD_RST_SHIFT, OMAP_GLOBAL_COLD_RST_SRC_ID_SHIFT },
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{ OMAP_GLOBALWARM_RST_SHIFT, OMAP_GLOBAL_WARM_RST_SRC_ID_SHIFT },
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{ OMAP24XX_SECU_VIOL_RST_SHIFT, OMAP_SECU_VIOL_RST_SRC_ID_SHIFT },
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{ OMAP24XX_MPU_WD_RST_SHIFT, OMAP_MPU_WD_RST_SRC_ID_SHIFT },
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{ OMAP24XX_SECU_WD_RST_SHIFT, OMAP_SECU_WD_RST_SRC_ID_SHIFT },
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{ OMAP24XX_EXTWMPU_RST_SHIFT, OMAP_EXTWARM_RST_SRC_ID_SHIFT },
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{ -1, -1 },
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};
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/**
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* omap2xxx_prm_read_reset_sources - return the last SoC reset source
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*
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* Return a u32 representing the last reset sources of the SoC. The
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* returned reset source bits are standardized across OMAP SoCs.
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*/
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static u32 omap2xxx_prm_read_reset_sources(void)
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{
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struct prm_reset_src_map *p;
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u32 r = 0;
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u32 v;
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v = omap2_prm_read_mod_reg(WKUP_MOD, OMAP2_RM_RSTST);
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p = omap2xxx_prm_reset_src_map;
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while (p->reg_shift >= 0 && p->std_shift >= 0) {
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if (v & (1 << p->reg_shift))
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r |= 1 << p->std_shift;
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p++;
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}
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return r;
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}
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/**
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* omap2xxx_pwrst_to_common_pwrst - convert OMAP2xxx pwrst to common pwrst
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* @omap2xxx_pwrst: OMAP2xxx hardware power state to convert
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*
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* Return the common power state bits corresponding to the OMAP2xxx
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* hardware power state bits @omap2xxx_pwrst, or -EINVAL upon error.
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*/
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static int omap2xxx_pwrst_to_common_pwrst(u8 omap2xxx_pwrst)
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{
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u8 pwrst;
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switch (omap2xxx_pwrst) {
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case OMAP24XX_PWRDM_POWER_OFF:
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pwrst = PWRDM_POWER_OFF;
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break;
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case OMAP24XX_PWRDM_POWER_RET:
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pwrst = PWRDM_POWER_RET;
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break;
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case OMAP24XX_PWRDM_POWER_ON:
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pwrst = PWRDM_POWER_ON;
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break;
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default:
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return -EINVAL;
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}
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return pwrst;
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}
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/**
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* omap2xxx_prm_dpll_reset - use DPLL reset to reboot the OMAP SoC
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*
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* Set the DPLL reset bit, which should reboot the SoC. This is the
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* recommended way to restart the SoC. No return value.
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*/
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static void omap2xxx_prm_dpll_reset(void)
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{
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omap2_prm_set_mod_reg_bits(OMAP_RST_DPLL3_MASK, WKUP_MOD,
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OMAP2_RM_RSTCTRL);
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/* OCP barrier */
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omap2_prm_read_mod_reg(WKUP_MOD, OMAP2_RM_RSTCTRL);
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}
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/**
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* omap2xxx_prm_clear_mod_irqs - clear wakeup status bits for a module
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* @module: PRM module to clear wakeups from
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* @regs: register offset to clear
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* @wkst_mask: wakeup status mask to clear
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*
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* Clears wakeup status bits for a given module, so that the device can
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* re-enter idle.
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*/
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static int omap2xxx_prm_clear_mod_irqs(s16 module, u8 regs, u32 wkst_mask)
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{
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u32 wkst;
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wkst = omap2_prm_read_mod_reg(module, regs);
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wkst &= wkst_mask;
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omap2_prm_write_mod_reg(wkst, module, regs);
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return 0;
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}
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int omap2xxx_clkdm_sleep(struct clockdomain *clkdm)
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{
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omap2_prm_set_mod_reg_bits(OMAP24XX_FORCESTATE_MASK,
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clkdm->pwrdm.ptr->prcm_offs,
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OMAP2_PM_PWSTCTRL);
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return 0;
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}
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int omap2xxx_clkdm_wakeup(struct clockdomain *clkdm)
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{
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omap2_prm_clear_mod_reg_bits(OMAP24XX_FORCESTATE_MASK,
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clkdm->pwrdm.ptr->prcm_offs,
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OMAP2_PM_PWSTCTRL);
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return 0;
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}
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static int omap2xxx_pwrdm_set_next_pwrst(struct powerdomain *pwrdm, u8 pwrst)
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{
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u8 omap24xx_pwrst;
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switch (pwrst) {
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case PWRDM_POWER_OFF:
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omap24xx_pwrst = OMAP24XX_PWRDM_POWER_OFF;
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break;
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case PWRDM_POWER_RET:
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omap24xx_pwrst = OMAP24XX_PWRDM_POWER_RET;
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break;
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case PWRDM_POWER_ON:
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omap24xx_pwrst = OMAP24XX_PWRDM_POWER_ON;
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break;
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default:
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return -EINVAL;
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}
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omap2_prm_rmw_mod_reg_bits(OMAP_POWERSTATE_MASK,
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(omap24xx_pwrst << OMAP_POWERSTATE_SHIFT),
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pwrdm->prcm_offs, OMAP2_PM_PWSTCTRL);
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return 0;
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}
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static int omap2xxx_pwrdm_read_next_pwrst(struct powerdomain *pwrdm)
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{
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u8 omap2xxx_pwrst;
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omap2xxx_pwrst = omap2_prm_read_mod_bits_shift(pwrdm->prcm_offs,
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OMAP2_PM_PWSTCTRL,
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OMAP_POWERSTATE_MASK);
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return omap2xxx_pwrst_to_common_pwrst(omap2xxx_pwrst);
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}
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static int omap2xxx_pwrdm_read_pwrst(struct powerdomain *pwrdm)
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{
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u8 omap2xxx_pwrst;
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omap2xxx_pwrst = omap2_prm_read_mod_bits_shift(pwrdm->prcm_offs,
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OMAP2_PM_PWSTST,
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OMAP_POWERSTATEST_MASK);
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return omap2xxx_pwrst_to_common_pwrst(omap2xxx_pwrst);
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}
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struct pwrdm_ops omap2_pwrdm_operations = {
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.pwrdm_set_next_pwrst = omap2xxx_pwrdm_set_next_pwrst,
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.pwrdm_read_next_pwrst = omap2xxx_pwrdm_read_next_pwrst,
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.pwrdm_read_pwrst = omap2xxx_pwrdm_read_pwrst,
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.pwrdm_set_logic_retst = omap2_pwrdm_set_logic_retst,
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.pwrdm_set_mem_onst = omap2_pwrdm_set_mem_onst,
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.pwrdm_set_mem_retst = omap2_pwrdm_set_mem_retst,
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.pwrdm_read_mem_pwrst = omap2_pwrdm_read_mem_pwrst,
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.pwrdm_read_mem_retst = omap2_pwrdm_read_mem_retst,
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.pwrdm_wait_transition = omap2_pwrdm_wait_transition,
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};
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/*
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*
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*/
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static struct prm_ll_data omap2xxx_prm_ll_data = {
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.read_reset_sources = &omap2xxx_prm_read_reset_sources,
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.assert_hardreset = &omap2_prm_assert_hardreset,
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.deassert_hardreset = &omap2_prm_deassert_hardreset,
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.is_hardreset_asserted = &omap2_prm_is_hardreset_asserted,
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.reset_system = &omap2xxx_prm_dpll_reset,
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.clear_mod_irqs = &omap2xxx_prm_clear_mod_irqs,
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};
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int __init omap2xxx_prm_init(const struct omap_prcm_init_data *data)
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{
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return prm_register(&omap2xxx_prm_ll_data);
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}
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static void __exit omap2xxx_prm_exit(void)
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{
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prm_unregister(&omap2xxx_prm_ll_data);
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}
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__exitcall(omap2xxx_prm_exit);
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