326 lines
5.9 KiB
Plaintext
326 lines
5.9 KiB
Plaintext
// SPDX-License-Identifier: GPL-2.0
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// Copyright (c) 2020 AMD Inc.
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// Author: Supreeth Venkatesh <supreeth.venkatesh@amd.com>
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/dts-v1/;
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#include "aspeed-g5.dtsi"
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#include <dt-bindings/gpio/aspeed-gpio.h>
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/ {
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model = "AMD EthanolX BMC";
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compatible = "amd,ethanolx-bmc", "aspeed,ast2500";
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memory@80000000 {
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reg = <0x80000000 0x20000000>;
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};
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reserved-memory {
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#address-cells = <1>;
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#size-cells = <1>;
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ranges;
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video_engine_memory: jpegbuffer {
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size = <0x02000000>; /* 32M */
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alignment = <0x01000000>;
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compatible = "shared-dma-pool";
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reusable;
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};
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};
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aliases {
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serial0 = &uart1;
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serial4 = &uart5;
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};
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chosen {
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stdout-path = &uart5;
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bootargs = "console=ttyS4,115200 earlycon";
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};
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leds {
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compatible = "gpio-leds";
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fault {
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gpios = <&gpio ASPEED_GPIO(A, 2) GPIO_ACTIVE_LOW>;
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};
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identify {
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gpios = <&gpio ASPEED_GPIO(A, 3) GPIO_ACTIVE_LOW>;
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};
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};
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iio-hwmon {
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compatible = "iio-hwmon";
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io-channels = <&adc 0>, <&adc 1>, <&adc 2>, <&adc 3>, <&adc 4>;
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};
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};
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&fmc {
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status = "okay";
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flash@0 {
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status = "okay";
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m25p,fast-read;
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#include "openbmc-flash-layout.dtsi"
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};
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};
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&mac0 {
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status = "okay";
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_rmii1_default>;
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clocks = <&syscon ASPEED_CLK_GATE_MAC1CLK>,
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<&syscon ASPEED_CLK_MAC1RCLK>;
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clock-names = "MACCLK", "RCLK";
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};
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&uart1 {
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//Host Console
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status = "okay";
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_txd1_default
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&pinctrl_rxd1_default>;
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};
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&uart5 {
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//BMC Console
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status = "okay";
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};
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&adc {
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status = "okay";
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_adc0_default
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&pinctrl_adc1_default
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&pinctrl_adc2_default
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&pinctrl_adc3_default
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&pinctrl_adc4_default>;
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};
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&gpio {
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status = "okay";
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gpio-line-names =
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/*A0-A7*/ "","","FAULT_LED","CHASSIS_ID_LED","","","","",
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/*B0-B7*/ "","","","","","","","",
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/*C0-C7*/ "CHASSIS_ID_BTN","INTRUDER","AC_LOSS","","","","","",
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/*D0-D7*/ "HDT_DBREQ","LOCAL_SPI_ROM_SEL","FPGA_SPI_ROM_SEL","JTAG_MUX_S",
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"JTAG_MUX_OE","HDT_SEL","ASERT_WARM_RST_BTN","FPGA_RSVD",
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/*E0-E7*/ "","","MON_P0_PWR_BTN","MON_P0_RST_BTN","MON_P0_NMI_BTN",
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"MON_P0_PWR_GOOD","MON_PWROK","MON_RESET",
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/*F0-F7*/ "MON_P0_PROCHOT","MON_P1_PROCHOT","MON_P0_THERMTRIP",
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"MON_P1_THERMTRIP","P0_PRESENT","P1_PRESENT","MON_ATX_PWR_OK","",
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/*G0-G7*/ "BRD_REV_ID_3","BRD_REV_ID_2","BRD_REV_ID_1","BRD_REV_ID_0",
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"P0_APML_ALERT","P1_APML_ALERT","FPGA ALERT","",
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/*H0-H7*/ "BRD_ID_0","BRD_ID_1","BRD_ID_2","BRD_ID_3",
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"PCIE_DISCONNECTED","USB_DISCONNECTED","SPARE_0","SPARE_1",
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/*I0-I7*/ "","","","","","","","",
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/*J0-J7*/ "","","","","","","","",
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/*K0-K7*/ "","","","","","","","",
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/*L0-L7*/ "","","","","","","","",
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/*M0-M7*/ "ASSERT_PWR_BTN","ASSERT_RST_BTN","ASSERT_NMI_BTN",
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"ASSERT_LOCAL_LOCK","ASSERT_P0_PROCHOT","ASSERT_P1_PROCHOT",
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"ASSERT_CLR_CMOS","ASSERT_BMC_READY",
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/*N0-N7*/ "","","","","","","","",
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/*O0-O7*/ "","","","","","","","",
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/*P0-P7*/ "P0_VDD_CORE_RUN_VRHOT","P0_VDD_SOC_RUN_VRHOT",
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"P0_VDD_MEM_ABCD_SUS_VRHOT","P0_VDD_MEM_EFGH_SUS_VRHOT",
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"P1_VDD_CORE_RUN_VRHOT","P1_VDD_SOC_RUN_VRHOT",
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"P1_VDD_MEM_ABCD_SUS_VRHOT","P1_VDD_MEM_EFGH_SUS_VRHOT",
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/*Q0-Q7*/ "","","","","","","","",
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/*R0-R7*/ "","","","","","","","",
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/*S0-S7*/ "","","","","","","","",
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/*T0-T7*/ "","","","","","","","",
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/*U0-U7*/ "","","","","","","","",
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/*V0-V7*/ "","","","","","","","",
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/*W0-W7*/ "","","","","","","","",
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/*X0-X7*/ "","","","","","","","",
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/*Y0-Y7*/ "","","","","","","","",
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/*Z0-Z7*/ "","","","","","","","",
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/*AA0-AA7*/ "","SENSOR THERM","","","","","","",
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/*AB0-AB7*/ "","","","","","","","",
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/*AC0-AC7*/ "","","","","","","","";
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};
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//APML for P0
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&i2c0 {
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status = "okay";
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};
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//APML for P1
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&i2c1 {
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status = "okay";
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};
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//FPGA
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&i2c2 {
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status = "okay";
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};
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//24LC128 EEPROM
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&i2c3 {
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status = "okay";
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eeprom@50 {
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compatible = "atmel,24c256";
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reg = <0x50>;
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pagesize = <64>;
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};
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};
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//P0 Power regulators
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&i2c4 {
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status = "okay";
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};
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//P1 Power regulators
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&i2c5 {
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status = "okay";
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};
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//P0/P1 Thermal diode
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&i2c6 {
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status = "okay";
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};
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// Thermal Sensors
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&i2c7 {
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status = "okay";
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lm75a@48 {
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compatible = "national,lm75a";
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reg = <0x48>;
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};
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lm75a@49 {
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compatible = "national,lm75a";
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reg = <0x49>;
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};
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lm75a@4a {
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compatible = "national,lm75a";
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reg = <0x4a>;
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};
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lm75a@4b {
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compatible = "national,lm75a";
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reg = <0x4b>;
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};
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lm75a@4c {
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compatible = "national,lm75a";
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reg = <0x4c>;
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};
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lm75a@4d {
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compatible = "national,lm75a";
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reg = <0x4d>;
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};
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lm75a@4e {
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compatible = "national,lm75a";
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reg = <0x4e>;
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};
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lm75a@4f {
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compatible = "national,lm75a";
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reg = <0x4f>;
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};
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};
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//BMC I2C
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&i2c8 {
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status = "okay";
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};
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&kcs1 {
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status = "okay";
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aspeed,lpc-io-reg = <0x60>;
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};
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&kcs2 {
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status = "okay";
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aspeed,lpc-io-reg = <0x62>;
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};
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&kcs3 {
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status = "okay";
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aspeed,lpc-io-reg = <0xCA2>;
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};
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&kcs4 {
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status = "okay";
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aspeed,lpc-io-reg = <0x97DE>;
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};
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&lpc_snoop {
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status = "okay";
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snoop-ports = <0x80>, <0x81>;
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};
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&lpc_ctrl {
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//Enable lpc clock
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status = "okay";
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};
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&pwm_tacho {
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status = "okay";
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_pwm0_default
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&pinctrl_pwm1_default
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&pinctrl_pwm2_default
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&pinctrl_pwm3_default
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&pinctrl_pwm4_default
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&pinctrl_pwm5_default
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&pinctrl_pwm6_default
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&pinctrl_pwm7_default>;
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fan@0 {
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reg = <0x00>;
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aspeed,fan-tach-ch = /bits/ 8 <0x00>;
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};
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fan@1 {
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reg = <0x01>;
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aspeed,fan-tach-ch = /bits/ 8 <0x01>;
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};
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fan@2 {
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reg = <0x02>;
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aspeed,fan-tach-ch = /bits/ 8 <0x02>;
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};
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fan@3 {
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reg = <0x03>;
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aspeed,fan-tach-ch = /bits/ 8 <0x03>;
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};
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fan@4 {
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reg = <0x04>;
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aspeed,fan-tach-ch = /bits/ 8 <0x04>;
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};
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fan@5 {
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reg = <0x05>;
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aspeed,fan-tach-ch = /bits/ 8 <0x05>;
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};
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fan@6 {
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reg = <0x06>;
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aspeed,fan-tach-ch = /bits/ 8 <0x06>;
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};
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fan@7 {
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reg = <0x07>;
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aspeed,fan-tach-ch = /bits/ 8 <0x07>;
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};
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};
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&video {
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status = "okay";
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memory-region = <&video_engine_memory>;
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};
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&vhub {
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status = "okay";
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};
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