162 lines
3.9 KiB
YAML
162 lines
3.9 KiB
YAML
# SPDX-License-Identifier: GPL-2.0
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%YAML 1.2
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---
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$id: http://devicetree.org/schemas/spi/spi-pl022.yaml#
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$schema: http://devicetree.org/meta-schemas/core.yaml#
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title: ARM PL022 SPI controller
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maintainers:
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- Linus Walleij <linus.walleij@linaro.org>
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allOf:
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- $ref: "spi-controller.yaml#"
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# We need a select here so we don't match all nodes with 'arm,primecell'
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select:
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properties:
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compatible:
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contains:
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const: arm,pl022
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required:
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- compatible
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properties:
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compatible:
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items:
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- const: arm,pl022
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- const: arm,primecell
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reg:
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maxItems: 1
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interrupts:
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maxItems: 1
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clocks:
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maxItems: 2
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clock-names:
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items:
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- const: sspclk
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- const: apb_pclk
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pl022,autosuspend-delay:
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description: delay in ms following transfer completion before the
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runtime power management system suspends the device. A setting of 0
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indicates no delay and the device will be suspended immediately.
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$ref: "/schemas/types.yaml#/definitions/uint32"
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pl022,rt:
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description: indicates the controller should run the message pump with realtime
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priority to minimise the transfer latency on the bus (boolean)
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type: boolean
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dmas:
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description:
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Two or more DMA channel specifiers following the convention outlined
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in bindings/dma/dma.txt
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minItems: 2
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maxItems: 32
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dma-names:
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description:
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There must be at least one channel named "tx" for transmit and named "rx"
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for receive.
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minItems: 2
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maxItems: 32
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additionalItems: true
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items:
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- const: rx
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- const: tx
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resets:
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maxItems: 1
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patternProperties:
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"^[a-zA-Z][a-zA-Z0-9,+\\-._]{0,63}@[0-9a-f]+$":
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type: object
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# SPI slave nodes must be children of the SPI master node and can
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# contain the following properties.
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properties:
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pl022,interface:
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description: SPI interface type
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$ref: "/schemas/types.yaml#/definitions/uint32"
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enum:
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- 0 # SPI
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- 1 # Texas Instruments Synchronous Serial Frame Format
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- 2 # Microwire (Half Duplex)
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pl022,com-mode:
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description: Specifies the transfer mode
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$ref: "/schemas/types.yaml#/definitions/uint32"
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enum:
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- 0 # interrupt mode
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- 1 # polling mode
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- 2 # DMA mode
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default: 1
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pl022,rx-level-trig:
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description: Rx FIFO watermark level
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$ref: "/schemas/types.yaml#/definitions/uint32"
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minimum: 0
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maximum: 4
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pl022,tx-level-trig:
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description: Tx FIFO watermark level
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$ref: "/schemas/types.yaml#/definitions/uint32"
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minimum: 0
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maximum: 4
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pl022,ctrl-len:
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description: Microwire interface - Control length
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$ref: "/schemas/types.yaml#/definitions/uint32"
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minimum: 0x03
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maximum: 0x1f
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pl022,wait-state:
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description: Microwire interface - Wait state
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$ref: "/schemas/types.yaml#/definitions/uint32"
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enum: [0, 1]
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pl022,duplex:
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description: Microwire interface - Full/Half duplex
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$ref: "/schemas/types.yaml#/definitions/uint32"
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enum: [0, 1]
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required:
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- compatible
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- reg
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- interrupts
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unevaluatedProperties: false
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examples:
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- |
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spi@e0100000 {
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compatible = "arm,pl022", "arm,primecell";
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reg = <0xe0100000 0x1000>;
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#address-cells = <1>;
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#size-cells = <0>;
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interrupts = <0 31 0x4>;
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dmas = <&dma_controller 23 1>,
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<&dma_controller 24 0>;
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dma-names = "rx", "tx";
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flash@1 {
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compatible = "st,m25p80";
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reg = <1>;
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spi-max-frequency = <12000000>;
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spi-cpol;
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spi-cpha;
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pl022,interface = <0>;
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pl022,com-mode = <0x2>;
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pl022,rx-level-trig = <0>;
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pl022,tx-level-trig = <0>;
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pl022,ctrl-len = <0x11>;
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pl022,wait-state = <0>;
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pl022,duplex = <0>;
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};
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};
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...
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