214 lines
5.3 KiB
YAML
214 lines
5.3 KiB
YAML
# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
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%YAML 1.2
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---
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$id: http://devicetree.org/schemas/soc/microchip/atmel,at91rm9200-tcb.yaml#
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$schema: http://devicetree.org/meta-schemas/core.yaml#
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title: Atmel Timer Counter Block
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maintainers:
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- Alexandre Belloni <alexandre.belloni@bootlin.com>
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description: |
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The Atmel (now Microchip) SoCs have timers named Timer Counter Block. Each
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timer has three channels with two counters each.
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properties:
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compatible:
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items:
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- enum:
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- atmel,at91rm9200-tcb
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- atmel,at91sam9x5-tcb
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- atmel,sama5d2-tcb
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- const: simple-mfd
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- const: syscon
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reg:
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maxItems: 1
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interrupts:
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description:
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List of interrupts. One interrupt per TCB channel if available or one
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interrupt for the TC block
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minItems: 1
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maxItems: 3
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clock-names:
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description:
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List of clock names. Always includes t0_clk and slow clk. Also includes
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t1_clk and t2_clk if a clock per channel is available.
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minItems: 2
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maxItems: 4
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clocks:
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minItems: 2
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maxItems: 4
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'#address-cells':
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const: 1
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'#size-cells':
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const: 0
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patternProperties:
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"^timer@[0-2]$":
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description: The timer block channels that are used as timers or counters.
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type: object
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properties:
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compatible:
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items:
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- enum:
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- atmel,tcb-timer
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- atmel,tcb-pwm
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- microchip,tcb-capture
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reg:
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description:
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List of channels to use for this particular timer. In Microchip TCB capture
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mode channels are registered as a counter devices, for the qdec mode TCB0's
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channel <0> and <1> are required.
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minItems: 1
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maxItems: 3
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required:
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- compatible
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- reg
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"^pwm@[0-2]$":
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description: The timer block channels that are used as PWMs.
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$ref: /schemas/pwm/pwm.yaml#
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type: object
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properties:
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compatible:
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const: atmel,tcb-pwm
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reg:
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description:
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TCB channel to use for this PWM.
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enum: [ 0, 1, 2 ]
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"#pwm-cells":
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description:
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The only third cell flag supported by this binding is
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PWM_POLARITY_INVERTED.
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const: 3
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required:
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- compatible
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- reg
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- "#pwm-cells"
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additionalProperties: false
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allOf:
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- if:
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properties:
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compatible:
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contains:
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const: atmel,sama5d2-tcb
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then:
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properties:
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clocks:
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minItems: 3
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maxItems: 3
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clock-names:
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items:
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- const: t0_clk
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- const: gclk
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- const: slow_clk
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else:
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properties:
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clocks:
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minItems: 2
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maxItems: 4
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clock-names:
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oneOf:
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- items:
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- const: t0_clk
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- const: slow_clk
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- items:
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- const: t0_clk
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- const: t1_clk
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- const: t2_clk
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- const: slow_clk
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required:
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- compatible
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- reg
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- interrupts
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- clocks
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- clock-names
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- '#address-cells'
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- '#size-cells'
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additionalProperties: false
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examples:
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- |
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/* One interrupt per TC block: */
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tcb0: timer@fff7c000 {
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compatible = "atmel,at91rm9200-tcb", "simple-mfd", "syscon";
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#address-cells = <1>;
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#size-cells = <0>;
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reg = <0xfff7c000 0x100>;
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interrupts = <18 4>;
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clocks = <&tcb0_clk>, <&clk32k>;
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clock-names = "t0_clk", "slow_clk";
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timer@0 {
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compatible = "atmel,tcb-timer";
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reg = <0>, <1>;
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};
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timer@2 {
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compatible = "atmel,tcb-timer";
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reg = <2>;
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};
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};
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/* One interrupt per TC channel in a TC block: */
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tcb1: timer@fffdc000 {
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compatible = "atmel,at91rm9200-tcb", "simple-mfd", "syscon";
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#address-cells = <1>;
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#size-cells = <0>;
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reg = <0xfffdc000 0x100>;
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interrupts = <26 4>, <27 4>, <28 4>;
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clocks = <&tcb1_clk>, <&clk32k>;
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clock-names = "t0_clk", "slow_clk";
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timer@0 {
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compatible = "atmel,tcb-timer";
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reg = <0>;
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};
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timer@1 {
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compatible = "atmel,tcb-timer";
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reg = <1>;
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};
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pwm@2 {
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compatible = "atmel,tcb-pwm";
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reg = <2>;
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#pwm-cells = <3>;
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};
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};
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/* TCB0 Capture with QDEC: */
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timer@f800c000 {
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compatible = "atmel,at91rm9200-tcb", "simple-mfd", "syscon";
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#address-cells = <1>;
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#size-cells = <0>;
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reg = <0xfff7c000 0x100>;
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interrupts = <18 4>;
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clocks = <&tcb0_clk>, <&clk32k>;
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clock-names = "t0_clk", "slow_clk";
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timer@0 {
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compatible = "microchip,tcb-capture";
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reg = <0>, <1>;
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};
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timer@2 {
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compatible = "atmel,tcb-timer";
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reg = <2>;
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};
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};
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