162 lines
4.0 KiB
YAML
162 lines
4.0 KiB
YAML
# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
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%YAML 1.2
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---
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$id: http://devicetree.org/schemas/pinctrl/nuvoton,wpcm450-pinctrl.yaml#
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$schema: http://devicetree.org/meta-schemas/core.yaml#
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title: Nuvoton WPCM450 pin control and GPIO
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maintainers:
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- Jonathan Neuschäfer <j.neuschaefer@gmx.net>
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properties:
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compatible:
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const: nuvoton,wpcm450-pinctrl
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reg:
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maxItems: 1
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'#address-cells':
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const: 1
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'#size-cells':
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const: 0
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patternProperties:
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# There are three kinds of subnodes:
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# 1. a GPIO controller node for each GPIO bank
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# 2. a pinmux node configures pin muxing for a group of pins (e.g. rmii2)
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# 3. a pinconf node configures properties of a single pin
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"^gpio@[0-7]$":
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type: object
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additionalProperties: false
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description:
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Eight GPIO banks (gpio@0 to gpio@7), that each contain between 14 and 18
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GPIOs. Some GPIOs support interrupts.
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properties:
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reg:
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minimum: 0
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maximum: 7
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gpio-controller: true
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"#gpio-cells":
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const: 2
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interrupt-controller: true
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"#interrupt-cells":
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const: 2
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interrupts:
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maxItems: 3
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description:
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The interrupts associated with this GPIO bank
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required:
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- reg
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- gpio-controller
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- '#gpio-cells'
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"^mux-":
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$ref: pinmux-node.yaml#
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properties:
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groups:
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description:
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One or more groups of pins to mux to a certain function
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items:
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enum: [ smb3, smb4, smb5, scs1, scs2, scs3, smb0, smb1, smb2, bsp,
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hsp1, hsp2, r1err, r1md, rmii2, r2err, r2md, kbcc, dvo,
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clko, smi, uinc, gspi, mben, xcs2, xcs1, sdio, sspi, fi0,
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fi1, fi2, fi3, fi4, fi5, fi6, fi7, fi8, fi9, fi10, fi11,
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fi12, fi13, fi14, fi15, pwm0, pwm1, pwm2, pwm3, pwm4, pwm5,
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pwm6, pwm7, hg0, hg1, hg2, hg3, hg4, hg5, hg6, hg7 ]
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function:
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description:
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The function that a group of pins is muxed to
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enum: [ smb3, smb4, smb5, scs1, scs2, scs3, smb0, smb1, smb2, bsp,
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hsp1, hsp2, r1err, r1md, rmii2, r2err, r2md, kbcc, dvo0,
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dvo1, dvo2, dvo3, dvo4, dvo5, dvo6, dvo7, clko, smi, uinc,
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gspi, mben, xcs2, xcs1, sdio, sspi, fi0, fi1, fi2, fi3, fi4,
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fi5, fi6, fi7, fi8, fi9, fi10, fi11, fi12, fi13, fi14, fi15,
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pwm0, pwm1, pwm2, pwm3, pwm4, pwm5, pwm6, pwm7, hg0, hg1,
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hg2, hg3, hg4, hg5, hg6, hg7, gpio ]
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dependencies:
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groups: [ function ]
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function: [ groups ]
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additionalProperties: false
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"^cfg-":
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$ref: pincfg-node.yaml#
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properties:
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pins:
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description:
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A list of pins to configure in certain ways, such as enabling
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debouncing
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items:
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pattern: "^gpio1?[0-9]{1,2}$"
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input-debounce: true
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additionalProperties: false
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required:
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- compatible
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- reg
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additionalProperties: false
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examples:
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- |
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#include <dt-bindings/interrupt-controller/irq.h>
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#include <dt-bindings/gpio/gpio.h>
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pinctrl: pinctrl@b8003000 {
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compatible = "nuvoton,wpcm450-pinctrl";
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reg = <0xb8003000 0x1000>;
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#address-cells = <1>;
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#size-cells = <0>;
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gpio0: gpio@0 {
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reg = <0>;
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gpio-controller;
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#gpio-cells = <2>;
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interrupts = <2 IRQ_TYPE_LEVEL_HIGH>,
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<3 IRQ_TYPE_LEVEL_HIGH>,
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<4 IRQ_TYPE_LEVEL_HIGH>;
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};
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mux-rmii2 {
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groups = "rmii2";
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function = "rmii2";
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};
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pinmux_uid: mux-uid {
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groups = "gspi", "sspi";
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function = "gpio";
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};
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pinctrl_uid: cfg-uid {
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pins = "gpio14";
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input-debounce = <1>;
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};
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};
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gpio-keys {
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compatible = "gpio-keys";
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_uid>, <&pinmux_uid>;
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button-uid {
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label = "UID";
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linux,code = <102>;
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gpios = <&gpio0 14 GPIO_ACTIVE_HIGH>;
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};
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};
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