411 lines
13 KiB
YAML
411 lines
13 KiB
YAML
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
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%YAML 1.2
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---
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$id: http://devicetree.org/schemas/pinctrl/mediatek,mt7986-pinctrl.yaml#
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$schema: http://devicetree.org/meta-schemas/core.yaml#
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title: Mediatek MT7986 Pin Controller
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maintainers:
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- Sean Wang <sean.wang@kernel.org>
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description: |+
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The MediaTek's MT7986 Pin controller is used to control SoC pins.
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properties:
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compatible:
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enum:
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- mediatek,mt7986a-pinctrl
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- mediatek,mt7986b-pinctrl
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reg:
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minItems: 8
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maxItems: 8
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reg-names:
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items:
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- const: gpio
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- const: iocfg_rt
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- const: iocfg_rb
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- const: iocfg_lt
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- const: iocfg_lb
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- const: iocfg_tr
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- const: iocfg_tl
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- const: eint
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gpio-controller: true
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"#gpio-cells":
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const: 2
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description: |
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Number of cells in GPIO specifier. Since the generic GPIO
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binding is used, the amount of cells must be specified as 2. See the below
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mentioned gpio binding representation for description of particular cells.
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gpio-ranges:
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minItems: 1
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maxItems: 5
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description: |
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GPIO valid number range.
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interrupt-controller: true
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interrupts:
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maxItems: 1
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"#interrupt-cells":
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const: 2
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allOf:
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- $ref: "pinctrl.yaml#"
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required:
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- compatible
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- reg
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- reg-names
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- gpio-controller
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- "#gpio-cells"
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patternProperties:
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'-pins$':
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type: object
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additionalProperties: false
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patternProperties:
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'.*mux.*':
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type: object
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additionalProperties: false
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description: |
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pinmux configuration nodes.
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The following table shows the effective values of "group", "function"
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properties and chip pinout pins
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groups function pins (in pin#)
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---------------------------------------------------------------------
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"watchdog" "watchdog" 0
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"wifi_led" "led" 1, 2
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"i2c" "i2c" 3, 4
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"uart1_0" "uart" 7, 8, 9, 10
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"uart1_rx_tx" "uart" 42, 43
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"uart1_cts_rts" "uart" 44, 45
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"pcie_clk" "pcie" 9
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"pcie_wake" "pcie" 10
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"spi1_0" "spi" 11, 12, 13, 14
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"pwm1_1" "pwm" 20,
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"pwm0" "pwm" 21,
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"pwm1_0" "pwm" 22,
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"snfi" "flash" 23, 24, 25, 26, 27, 28
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"spi1_2" "spi" 29, 30, 31, 32
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"emmc_45" "emmc" 22, 23, 24, 25, 26, 27, 28, 29, 30,
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31, 32
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"spi1_1" "spi" 23, 24, 25, 26
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"uart1_2_rx_tx" "uart" 29, 30
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"uart1_2_cts_rts" "uart" 31, 32
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"uart1_1" "uart" 23, 24, 25, 26
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"uart2_0_rx_tx" "uart" 29, 30
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"uart2_0_cts_rts" "uart" 31, 32
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"spi0" "spi" 33, 34, 35, 36
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"spi0_wp_hold" "spi" 37, 38
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"uart1_3_rx_tx" "uart" 35, 36
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"uart1_3_cts_rts" "uart" 37, 38
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"uart2_1" "uart" 33, 34, 35, 36
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"spi1_3" "spi" 33, 34, 35, 36
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"uart0" "uart" 39, 40
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"pcie_pereset" "pcie" 41
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"uart1" "uart" 42, 43, 44, 45
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"uart2" "uart" 46, 47, 48, 49
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"emmc_51" "emmc" 50, 51, 52, 53, 54, 55, 56, 57, 57,
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59, 60, 61
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"pcm" "audio" 62, 63, 64, 65
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"i2s" "audio" 62, 63, 64, 65
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"switch_int" "eth" 66
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"mdc_mdio" "eth" 67
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"wf_2g" "wifi" 74, 75, 76, 77, 78, 79, 80, 81, 82, 83
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"wf_5g" "wifi" 91, 92, 93, 94, 95, 96, 97, 98, 99, 100
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"wf_dbdc" "wifi" 74, 75, 76, 77, 78, 79, 80, 81, 82, 83,
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84, 85
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$ref: "/schemas/pinctrl/pinmux-node.yaml"
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properties:
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function:
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description: |
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A string containing the name of the function to mux to the group.
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There is no "audio", "pcie" functions on mt7986b, you can only use
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those functions on mt7986a.
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enum: [audio, emmc, eth, i2c, led, flash, pcie, pwm, spi, uart,
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watchdog, wifi]
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groups:
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description: |
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An array of strings. Each string contains the name of a group.
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There is no "pcie_pereset", "uart1", "uart2" "emmc_51", "pcm",
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and "i2s" groups on mt7986b, you can only use those groups on
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mt7986a.
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required:
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- function
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- groups
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allOf:
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- if:
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properties:
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function:
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const: audio
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then:
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properties:
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groups:
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enum: [pcm, i2s]
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- if:
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properties:
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function:
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const: emmc
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then:
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properties:
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groups:
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enum: [emmc_45, emmc_51]
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- if:
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properties:
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function:
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const: eth
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then:
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properties:
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groups:
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enum: [switch_int, mdc_mdio]
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- if:
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properties:
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function:
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const: i2c
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then:
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properties:
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groups:
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enum: [i2c]
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- if:
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properties:
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function:
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const: led
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then:
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properties:
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groups:
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enum: [wifi_led]
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- if:
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properties:
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function:
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const: flash
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then:
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properties:
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groups:
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enum: [snfi]
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- if:
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properties:
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function:
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const: pcie
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then:
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properties:
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groups:
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enum: [pcie_clk, pcie_wake, pcie_pereset]
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- if:
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properties:
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function:
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const: pwm
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then:
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properties:
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groups:
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enum: [pwm0, pwm1_0, pwm1_1]
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- if:
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properties:
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function:
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const: spi
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then:
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properties:
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groups:
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enum: [spi0, spi0_wp_hold, spi1_0, spi1_1, spi1_2, spi1_3]
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- if:
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properties:
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function:
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const: uart
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then:
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properties:
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groups:
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items:
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enum: [uart1_0, uart1_rx_tx, uart1_cts_rts, uart1_1,
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uart1_2_rx_tx, uart1_2_cts_rts, uart1_3_rx_tx,
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uart1_3_cts_rts, uart2_0_rx_tx, uart2_0_cts_rts,
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uart2_1, uart0, uart1, uart2]
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maxItems: 2
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- if:
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properties:
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function:
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const: watchdog
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then:
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properties:
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groups:
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enum: [watchdog]
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- if:
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properties:
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function:
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const: wifi
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then:
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properties:
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groups:
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items:
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enum: [wf_2g, wf_5g, wf_dbdc]
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maxItems: 3
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'.*conf.*':
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type: object
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additionalProperties: false
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description: |
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pinconf configuration nodes.
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$ref: "/schemas/pinctrl/pincfg-node.yaml"
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properties:
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pins:
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description: |
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An array of strings. Each string contains the name of a pin.
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There is no PIN 41 to PIN 65 above on mt7686b, you can only use
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those pins on mt7986a.
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items:
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enum: [SYS_WATCHDOG, WF2G_LED, WF5G_LED, I2C_SCL, I2C_SDA, GPIO_0,
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GPIO_1, GPIO_2, GPIO_3, GPIO_4, GPIO_5, GPIO_6, GPIO_7,
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GPIO_8, GPIO_9, GPIO_10, GPIO_11, GPIO_12, GPIO_13, GPIO_14,
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GPIO_15, PWM0, PWM1, SPI0_CLK, SPI0_MOSI, SPI0_MISO, SPI0_CS,
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SPI0_HOLD, SPI0_WP, SPI1_CLK, SPI1_MOSI, SPI1_MISO, SPI1_CS,
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SPI2_CLK, SPI2_MOSI, SPI2_MISO, SPI2_CS, SPI2_HOLD, SPI2_WP,
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UART0_RXD, UART0_TXD, PCIE_PERESET_N, UART1_RXD, UART1_TXD,
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UART1_CTS, UART1_RTS, UART2_RXD, UART2_TXD, UART2_CTS,
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UART2_RTS, EMMC_DATA_0, EMMC_DATA_1, EMMC_DATA_2,
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EMMC_DATA_3, EMMC_DATA_4, EMMC_DATA_5, EMMC_DATA_6,
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EMMC_DATA_7, EMMC_CMD, EMMC_CK, EMMC_DSL, EMMC_RSTB, PCM_DTX,
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PCM_DRX, PCM_CLK, PCM_FS, MT7531_INT, SMI_MDC, SMI_MDIO,
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WF0_DIG_RESETB, WF0_CBA_RESETB, WF0_XO_REQ, WF0_TOP_CLK,
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WF0_TOP_DATA, WF0_HB1, WF0_HB2, WF0_HB3, WF0_HB4, WF0_HB0,
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WF0_HB0_B, WF0_HB5, WF0_HB6, WF0_HB7, WF0_HB8, WF0_HB9,
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WF0_HB10, WF1_DIG_RESETB, WF1_CBA_RESETB, WF1_XO_REQ,
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WF1_TOP_CLK, WF1_TOP_DATA, WF1_HB1, WF1_HB2, WF1_HB3,
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WF1_HB4, WF1_HB0, WF1_HB0_B, WF1_HB5, WF1_HB6, WF1_HB7,
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WF1_HB8]
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maxItems: 101
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bias-disable: true
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bias-pull-up: true
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bias-pull-down: true
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input-enable: true
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input-disable: true
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output-enable: true
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output-low: true
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output-high: true
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input-schmitt-enable: true
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input-schmitt-disable: true
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drive-strength:
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enum: [2, 4, 6, 8, 10, 12, 14, 16]
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mediatek,pull-up-adv:
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description: |
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Valid arguments for 'mediatek,pull-up-adv' are '0', '1', '2', '3'
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Pull up setings for 2 pull resistors, R0 and R1. Valid arguments
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are described as below:
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0: (R1, R0) = (0, 0) which means R1 disabled and R0 disabled.
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1: (R1, R0) = (0, 1) which means R1 disabled and R0 enabled.
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2: (R1, R0) = (1, 0) which means R1 enabled and R0 disabled.
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3: (R1, R0) = (1, 1) which means R1 enabled and R0 enabled.
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$ref: /schemas/types.yaml#/definitions/uint32
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enum: [0, 1, 2, 3]
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mediatek,pull-down-adv:
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description: |
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Valid arguments for 'mediatek,pull-up-adv' are '0', '1', '2', '3'
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Pull down setings for 2 pull resistors, R0 and R1. Valid arguments
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are described as below:
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0: (R1, R0) = (0, 0) which means R1 disabled and R0 disabled.
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1: (R1, R0) = (0, 1) which means R1 disabled and R0 enabled.
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2: (R1, R0) = (1, 0) which means R1 enabled and R0 disabled.
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3: (R1, R0) = (1, 1) which means R1 enabled and R0 enabled.
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$ref: /schemas/types.yaml#/definitions/uint32
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enum: [0, 1, 2, 3]
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required:
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- pins
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additionalProperties: false
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examples:
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- |
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#include <dt-bindings/interrupt-controller/irq.h>
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#include <dt-bindings/interrupt-controller/arm-gic.h>
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soc {
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#address-cells = <2>;
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#size-cells = <2>;
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pio: pinctrl@1001f000 {
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compatible = "mediatek,mt7986a-pinctrl";
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reg = <0 0x1001f000 0 0x1000>,
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<0 0x11c30000 0 0x1000>,
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<0 0x11c40000 0 0x1000>,
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<0 0x11e20000 0 0x1000>,
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<0 0x11e30000 0 0x1000>,
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<0 0x11f00000 0 0x1000>,
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<0 0x11f10000 0 0x1000>,
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<0 0x1000b000 0 0x1000>;
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reg-names = "gpio", "iocfg_rt", "iocfg_rb", "iocfg_lt",
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"iocfg_lb", "iocfg_tr", "iocfg_tl", "eint";
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gpio-controller;
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#gpio-cells = <2>;
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gpio-ranges = <&pio 0 0 100>;
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interrupt-controller;
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interrupts = <GIC_SPI 225 IRQ_TYPE_LEVEL_HIGH>;
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interrupt-parent = <&gic>;
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#interrupt-cells = <2>;
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pcie_pins: pcie-pins {
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mux {
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function = "pcie";
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groups = "pcie_clk", "pcie_wake", "pcie_pereset";
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};
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};
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pwm_pins: pwm-pins {
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mux {
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function = "pwm";
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groups = "pwm0", "pwm1_0";
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};
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};
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spi0_pins: spi0-pins {
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mux {
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function = "spi";
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groups = "spi0", "spi0_wp_hold";
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};
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};
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uart1_pins: uart1-pins {
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mux {
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function = "uart";
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groups = "uart1";
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};
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};
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uart1_3_pins: uart1-3-pins {
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mux {
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function = "uart";
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groups = "uart1_3_rx_tx", "uart1_3_cts_rts";
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};
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};
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uart2_pins: uart2-pins {
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mux {
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function = "uart";
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groups = "uart2";
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};
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};
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};
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};
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