137 lines
3.5 KiB
YAML
137 lines
3.5 KiB
YAML
# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
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%YAML 1.2
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---
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$id: http://devicetree.org/schemas/pinctrl/intel,pinctrl-keembay.yaml#
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$schema: http://devicetree.org/meta-schemas/core.yaml#
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title: Intel Keem Bay pin controller
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maintainers:
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- Lakshmi Sowjanya D <lakshmi.sowjanya.d@intel.com>
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description: |
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Intel Keem Bay SoC integrates a pin controller which enables control
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of pin directions, input/output values and configuration
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for a total of 80 pins.
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properties:
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compatible:
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const: intel,keembay-pinctrl
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reg:
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maxItems: 2
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gpio-controller: true
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'#gpio-cells':
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const: 2
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ngpios:
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description: The number of GPIOs exposed.
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const: 80
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interrupts:
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description:
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Specifies the interrupt lines to be used by the controller.
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Each interrupt line is shared by upto 4 GPIO lines.
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maxItems: 8
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interrupt-controller: true
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'#interrupt-cells':
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const: 2
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patternProperties:
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'^gpio@[0-9a-f]*$':
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type: object
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additionalProperties: false
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description:
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Child nodes can be specified to contain pin configuration information,
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which can then be utilized by pinctrl client devices.
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The following properties are supported.
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properties:
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pins:
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description: |
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The name(s) of the pins to be configured in the child node.
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Supported pin names are "GPIO0" up to "GPIO79".
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bias-disable: true
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bias-pull-down: true
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bias-pull-up: true
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drive-strength:
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description: IO pads drive strength in milli Ampere.
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enum: [2, 4, 8, 12]
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bias-bus-hold:
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type: boolean
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input-schmitt-enable:
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type: boolean
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slew-rate:
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description: GPIO slew rate control.
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0 - Fast(~100MHz)
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1 - Slow(~50MHz)
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enum: [0, 1]
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additionalProperties: false
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required:
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- compatible
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- reg
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- gpio-controller
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- ngpios
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- '#gpio-cells'
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- interrupts
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- interrupt-controller
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- '#interrupt-cells'
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examples:
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- |
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#include <dt-bindings/interrupt-controller/arm-gic.h>
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#include <dt-bindings/interrupt-controller/irq.h>
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// Example 1
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gpio@0 {
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compatible = "intel,keembay-pinctrl";
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reg = <0x600b0000 0x88>,
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<0x600b0190 0x1ac>;
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gpio-controller;
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ngpios = <0x50>;
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#gpio-cells = <0x2>;
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interrupts = <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>;
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interrupt-controller;
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#interrupt-cells = <2>;
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};
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// Example 2
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gpio@1 {
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compatible = "intel,keembay-pinctrl";
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reg = <0x600c0000 0x88>,
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<0x600c0190 0x1ac>;
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gpio-controller;
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ngpios = <0x50>;
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#gpio-cells = <0x2>;
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interrupts = <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>;
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interrupt-controller;
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#interrupt-cells = <2>;
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};
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