108 lines
2.5 KiB
YAML
108 lines
2.5 KiB
YAML
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
|
|
%YAML 1.2
|
|
---
|
|
$id: http://devicetree.org/schemas/net/mediatek,star-emac.yaml#
|
|
$schema: http://devicetree.org/meta-schemas/core.yaml#
|
|
|
|
title: MediaTek STAR Ethernet MAC Controller
|
|
|
|
maintainers:
|
|
- Bartosz Golaszewski <bgolaszewski@baylibre.com>
|
|
|
|
description:
|
|
This Ethernet MAC is used on the MT8* family of SoCs from MediaTek.
|
|
It's compliant with 802.3 standards and supports half- and full-duplex
|
|
modes with flow-control as well as CRC offloading and VLAN tags.
|
|
|
|
allOf:
|
|
- $ref: "ethernet-controller.yaml#"
|
|
|
|
properties:
|
|
compatible:
|
|
enum:
|
|
- mediatek,mt8516-eth
|
|
- mediatek,mt8518-eth
|
|
- mediatek,mt8175-eth
|
|
- mediatek,mt8365-eth
|
|
|
|
reg:
|
|
maxItems: 1
|
|
|
|
interrupts:
|
|
maxItems: 1
|
|
|
|
clocks:
|
|
minItems: 3
|
|
maxItems: 3
|
|
|
|
clock-names:
|
|
additionalItems: false
|
|
items:
|
|
- const: core
|
|
- const: reg
|
|
- const: trans
|
|
|
|
mediatek,pericfg:
|
|
$ref: /schemas/types.yaml#/definitions/phandle
|
|
description:
|
|
Phandle to the device containing the PERICFG register range. This is used
|
|
to control the MII mode.
|
|
|
|
mediatek,rmii-rxc:
|
|
type: boolean
|
|
description:
|
|
If present, indicates that the RMII reference clock, which is from external
|
|
PHYs, is connected to RXC pin. Otherwise, is connected to TXC pin.
|
|
|
|
mediatek,rxc-inverse:
|
|
type: boolean
|
|
description:
|
|
If present, indicates that clock on RXC pad will be inversed.
|
|
|
|
mediatek,txc-inverse:
|
|
type: boolean
|
|
description:
|
|
If present, indicates that clock on TXC pad will be inversed.
|
|
|
|
mdio:
|
|
$ref: mdio.yaml#
|
|
unevaluatedProperties: false
|
|
|
|
required:
|
|
- compatible
|
|
- reg
|
|
- interrupts
|
|
- clocks
|
|
- clock-names
|
|
- mediatek,pericfg
|
|
- phy-handle
|
|
|
|
unevaluatedProperties: false
|
|
|
|
examples:
|
|
- |
|
|
#include <dt-bindings/interrupt-controller/arm-gic.h>
|
|
#include <dt-bindings/clock/mt8516-clk.h>
|
|
|
|
ethernet: ethernet@11180000 {
|
|
compatible = "mediatek,mt8516-eth";
|
|
reg = <0x11180000 0x1000>;
|
|
mediatek,pericfg = <&pericfg>;
|
|
interrupts = <GIC_SPI 111 IRQ_TYPE_LEVEL_LOW>;
|
|
clocks = <&topckgen CLK_TOP_RG_ETH>,
|
|
<&topckgen CLK_TOP_66M_ETH>,
|
|
<&topckgen CLK_TOP_133M_ETH>;
|
|
clock-names = "core", "reg", "trans";
|
|
phy-handle = <ð_phy>;
|
|
phy-mode = "rmii";
|
|
|
|
mdio {
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
|
|
eth_phy: ethernet-phy@0 {
|
|
reg = <0>;
|
|
};
|
|
};
|
|
};
|