34 lines
1.2 KiB
Plaintext
34 lines
1.2 KiB
Plaintext
Hisilicon Hi655x Power Management Integrated Circuit (PMIC)
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The hardware layout for access PMIC Hi655x from AP SoC Hi6220.
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Between PMIC Hi655x and Hi6220, the physical signal channel is SSI.
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We can use memory-mapped I/O to communicate.
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+----------------+ +-------------+
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| | | |
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| Hi6220 | SSI bus | Hi655x |
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| |-------------| |
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| |(REGMAP_MMIO)| |
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+----------------+ +-------------+
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Required properties:
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- compatible: Should be "hisilicon,hi655x-pmic".
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- reg: Base address of PMIC on Hi6220 SoC.
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- interrupt-controller: Hi655x has internal IRQs (has own IRQ domain).
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- pmic-gpios: The GPIO used by PMIC IRQ.
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- #clock-cells: From common clock binding; shall be set to 0
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Optional properties:
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- clock-output-names: From common clock binding to override the
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default output clock name
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Example:
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pmic: pmic@f8000000 {
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compatible = "hisilicon,hi655x-pmic";
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reg = <0x0 0xf8000000 0x0 0x1000>;
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interrupt-controller;
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#interrupt-cells = <2>;
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pmic-gpios = <&gpio1 2 GPIO_ACTIVE_HIGH>;
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#clock-cells = <0>;
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}
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