173 lines
4.8 KiB
YAML
173 lines
4.8 KiB
YAML
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
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%YAML 1.2
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---
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$id: http://devicetree.org/schemas/media/nxp,imx8mq-mipi-csi2.yaml#
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$schema: http://devicetree.org/meta-schemas/core.yaml#
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title: NXP i.MX8MQ MIPI CSI-2 receiver
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maintainers:
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- Martin Kepplinger <martin.kepplinger@puri.sm>
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description: |-
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This binding covers the CSI-2 RX PHY and host controller included in the
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NXP i.MX8MQ SoC. It handles the sensor/image input and process for all the
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input imaging devices.
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properties:
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compatible:
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enum:
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- fsl,imx8mq-mipi-csi2
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reg:
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maxItems: 1
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clocks:
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items:
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- description: core is the RX Controller Core Clock input. This clock
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must be exactly equal to or faster than the receive
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byteclock from the RX DPHY.
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- description: esc is the Rx Escape Clock. This must be the same escape
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clock that the RX DPHY receives.
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- description: ui is the pixel clock (phy_ref up to 333Mhz).
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See the reference manual for details.
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clock-names:
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items:
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- const: core
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- const: esc
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- const: ui
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power-domains:
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maxItems: 1
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resets:
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items:
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- description: CORE_RESET reset register bit definition
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- description: PHY_REF_RESET reset register bit definition
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- description: ESC_RESET reset register bit definition
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fsl,mipi-phy-gpr:
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description: |
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The phandle to the imx8mq syscon iomux-gpr with the register
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for setting RX_ENABLE for the mipi receiver.
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The format should be as follows:
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<gpr req_gpr>
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gpr is the phandle to general purpose register node.
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req_gpr is the gpr register offset of RX_ENABLE for the mipi phy.
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$ref: /schemas/types.yaml#/definitions/phandle-array
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items:
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- items:
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- description: The 'gpr' is the phandle to general purpose register node.
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- description: The 'req_gpr' is the gpr register offset containing
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CSI2_1_RX_ENABLE or CSI2_2_RX_ENABLE respectively.
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maximum: 0xff
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interconnects:
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maxItems: 1
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interconnect-names:
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const: dram
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ports:
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$ref: /schemas/graph.yaml#/properties/ports
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properties:
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port@0:
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$ref: /schemas/graph.yaml#/$defs/port-base
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unevaluatedProperties: false
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description:
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Input port node, single endpoint describing the CSI-2 transmitter.
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properties:
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endpoint:
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$ref: video-interfaces.yaml#
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unevaluatedProperties: false
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properties:
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data-lanes:
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minItems: 1
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items:
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- const: 1
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- const: 2
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- const: 3
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- const: 4
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required:
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- data-lanes
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port@1:
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$ref: /schemas/graph.yaml#/properties/port
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description:
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Output port node
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required:
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- port@0
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- port@1
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required:
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- compatible
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- reg
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- clocks
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- clock-names
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- power-domains
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- resets
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- fsl,mipi-phy-gpr
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- ports
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additionalProperties: false
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examples:
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- |
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#include <dt-bindings/clock/imx8mq-clock.h>
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#include <dt-bindings/interconnect/imx8mq.h>
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#include <dt-bindings/reset/imx8mq-reset.h>
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csi@30a70000 {
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compatible = "fsl,imx8mq-mipi-csi2";
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reg = <0x30a70000 0x1000>;
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clocks = <&clk IMX8MQ_CLK_CSI1_CORE>,
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<&clk IMX8MQ_CLK_CSI1_ESC>,
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<&clk IMX8MQ_CLK_CSI1_PHY_REF>;
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clock-names = "core", "esc", "ui";
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assigned-clocks = <&clk IMX8MQ_CLK_CSI1_CORE>,
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<&clk IMX8MQ_CLK_CSI1_PHY_REF>,
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<&clk IMX8MQ_CLK_CSI1_ESC>;
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assigned-clock-rates = <266000000>, <200000000>, <66000000>;
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assigned-clock-parents = <&clk IMX8MQ_SYS1_PLL_266M>,
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<&clk IMX8MQ_SYS2_PLL_1000M>,
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<&clk IMX8MQ_SYS1_PLL_800M>;
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power-domains = <&pgc_mipi_csi1>;
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resets = <&src IMX8MQ_RESET_MIPI_CSI1_CORE_RESET>,
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<&src IMX8MQ_RESET_MIPI_CSI1_PHY_REF_RESET>,
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<&src IMX8MQ_RESET_MIPI_CSI1_ESC_RESET>;
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fsl,mipi-phy-gpr = <&iomuxc_gpr 0x88>;
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interconnects = <&noc IMX8MQ_ICM_CSI1 &noc IMX8MQ_ICS_DRAM>;
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interconnect-names = "dram";
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ports {
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#address-cells = <1>;
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#size-cells = <0>;
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port@0 {
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reg = <0>;
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imx8mm_mipi_csi_in: endpoint {
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remote-endpoint = <&imx477_out>;
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data-lanes = <1 2 3 4>;
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};
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};
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port@1 {
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reg = <1>;
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imx8mm_mipi_csi_out: endpoint {
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remote-endpoint = <&csi_in>;
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};
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};
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};
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};
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...
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