164 lines
5.9 KiB
YAML
164 lines
5.9 KiB
YAML
# SPDX-License-Identifier: (GPL-2.0-only or BSD-2-Clause)
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%YAML 1.2
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---
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$id: http://devicetree.org/schemas/interrupt-controller/ti,pruss-intc.yaml#
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$schema: http://devicetree.org/meta-schemas/core.yaml#
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title: TI PRU-ICSS Local Interrupt Controller
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maintainers:
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- Suman Anna <s-anna@ti.com>
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description: |
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Each PRU-ICSS has a single interrupt controller instance that is common
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to all the PRU cores. Most interrupt controllers can route 64 input events
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which are then mapped to 10 possible output interrupts through two levels
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of mapping. The input events can be triggered by either the PRUs and/or
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various other PRUSS internal and external peripherals. The first 2 output
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interrupts (0, 1) are fed exclusively to the internal PRU cores, with the
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remaining 8 (2 through 9) connected to external interrupt controllers
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including the MPU and/or other PRUSS instances, DSPs or devices.
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The property "ti,irqs-reserved" is used for denoting the connection
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differences on the output interrupts 2 through 9. If this property is not
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defined, it implies that all the PRUSS INTC output interrupts 2 through 9
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(host_intr0 through host_intr7) are connected exclusively to the Arm interrupt
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controller.
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The K3 family of SoCs can handle 160 input events that can be mapped to 20
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different possible output interrupts. The additional output interrupts (10
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through 19) are connected to new sub-modules within the ICSSG instances.
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This interrupt-controller node should be defined as a child node of the
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corresponding PRUSS node. The node should be named "interrupt-controller".
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properties:
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$nodename:
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pattern: "^interrupt-controller@[0-9a-f]+$"
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compatible:
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enum:
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- ti,pruss-intc
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- ti,icssg-intc
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description: |
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Use "ti,pruss-intc" for OMAP-L13x/AM18x/DA850 SoCs,
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AM335x family of SoCs,
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AM437x family of SoCs,
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AM57xx family of SoCs
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66AK2G family of SoCs
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Use "ti,icssg-intc" for K3 AM65x, J721E and AM64x family of SoCs
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reg:
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maxItems: 1
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interrupts:
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minItems: 1
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maxItems: 8
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description: |
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All the interrupts generated towards the main host processor in the SoC.
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A shared interrupt can be skipped if the desired destination and usage is
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by a different processor/device.
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interrupt-names:
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minItems: 1
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maxItems: 8
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items:
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pattern: host_intr[0-7]
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description: |
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Should use one of the above names for each valid host event interrupt
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connected to Arm interrupt controller, the name should match the
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corresponding host event interrupt number.
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interrupt-controller: true
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"#interrupt-cells":
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const: 3
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description: |
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Client users shall use the PRU System event number (the interrupt source
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that the client is interested in) [cell 1], PRU channel [cell 2] and PRU
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host_event (target) [cell 3] as the value of the interrupts property in
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their node. The system events can be mapped to some output host
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interrupts through 2 levels of many-to-one mapping i.e. events to channel
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mapping and channels to host interrupts so through this property entire
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mapping is provided.
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ti,irqs-reserved:
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$ref: /schemas/types.yaml#/definitions/uint8
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description: |
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Bitmask of host interrupts between 0 and 7 (corresponding to PRUSS INTC
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output interrupts 2 through 9) that are not connected to the Arm interrupt
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controller or are shared and used by other devices or processors in the
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SoC. Define this property when any of 8 interrupts should not be handled
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by Arm interrupt controller.
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Eg: - AM437x and 66AK2G SoCs do not have "host_intr5" interrupt
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connected to MPU
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- AM65x and J721E SoCs have "host_intr5", "host_intr6" and
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"host_intr7" interrupts connected to MPU, and other ICSSG
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instances.
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- AM64x SoCs have all the 8 host interrupts connected to various
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other SoC entities
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required:
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- compatible
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- reg
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- interrupts
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- interrupt-names
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- interrupt-controller
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- "#interrupt-cells"
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additionalProperties: false
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examples:
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- |
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/* AM33xx PRU-ICSS */
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pruss: pruss@0 {
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compatible = "ti,am3356-pruss";
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reg = <0x0 0x80000>;
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#address-cells = <1>;
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#size-cells = <1>;
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ranges;
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pruss_intc: interrupt-controller@20000 {
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compatible = "ti,pruss-intc";
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reg = <0x20000 0x2000>;
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interrupts = <20 21 22 23 24 25 26 27>;
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interrupt-names = "host_intr0", "host_intr1",
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"host_intr2", "host_intr3",
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"host_intr4", "host_intr5",
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"host_intr6", "host_intr7";
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interrupt-controller;
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#interrupt-cells = <3>;
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};
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};
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- |
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/* AM4376 PRU-ICSS */
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#include <dt-bindings/interrupt-controller/arm-gic.h>
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pruss@0 {
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compatible = "ti,am4376-pruss1";
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reg = <0x0 0x40000>;
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#address-cells = <1>;
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#size-cells = <1>;
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ranges;
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interrupt-controller@20000 {
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compatible = "ti,pruss-intc";
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reg = <0x20000 0x2000>;
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interrupt-controller;
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#interrupt-cells = <3>;
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interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>;
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interrupt-names = "host_intr0", "host_intr1",
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"host_intr2", "host_intr3",
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"host_intr4",
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"host_intr6", "host_intr7";
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ti,irqs-reserved = /bits/ 8 <0x20>; /* BIT(5) */
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};
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};
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