107 lines
3.3 KiB
YAML
107 lines
3.3 KiB
YAML
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
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%YAML 1.2
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---
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$id: http://devicetree.org/schemas/dma/st,stm32-mdma.yaml#
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$schema: http://devicetree.org/meta-schemas/core.yaml#
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title: STMicroelectronics STM32 MDMA Controller bindings
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description: |
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The STM32 MDMA is a general-purpose direct memory access controller capable of
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supporting 64 independent DMA channels with 256 HW requests.
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DMA clients connected to the STM32 MDMA controller must use the format
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described in the dma.txt file, using a five-cell specifier for each channel:
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a phandle to the MDMA controller plus the following five integer cells:
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1. The request line number
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2. The priority level
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0x0: Low
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0x1: Medium
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0x2: High
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0x3: Very high
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3. A 32bit mask specifying the DMA channel configuration
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-bit 0-1: Source increment mode
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0x0: Source address pointer is fixed
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0x2: Source address pointer is incremented after each data transfer
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0x3: Source address pointer is decremented after each data transfer
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-bit 2-3: Destination increment mode
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0x0: Destination address pointer is fixed
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0x2: Destination address pointer is incremented after each data transfer
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0x3: Destination address pointer is decremented after each data transfer
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-bit 8-9: Source increment offset size
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0x0: byte (8bit)
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0x1: half-word (16bit)
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0x2: word (32bit)
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0x3: double-word (64bit)
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-bit 10-11: Destination increment offset size
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0x0: byte (8bit)
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0x1: half-word (16bit)
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0x2: word (32bit)
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0x3: double-word (64bit)
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-bit 25-18: The number of bytes to be transferred in a single transfer
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(min = 1 byte, max = 128 bytes)
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-bit 29:28: Trigger Mode
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0x00: Each MDMA request triggers a buffer transfer (max 128 bytes)
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0x1: Each MDMA request triggers a block transfer (max 64K bytes)
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0x2: Each MDMA request triggers a repeated block transfer
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0x3: Each MDMA request triggers a linked list transfer
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4. A 32bit value specifying the register to be used to acknowledge the request
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if no HW ack signal is used by the MDMA client
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5. A 32bit mask specifying the value to be written to acknowledge the request
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if no HW ack signal is used by the MDMA client
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maintainers:
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- Amelie Delaunay <amelie.delaunay@foss.st.com>
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allOf:
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- $ref: "dma-controller.yaml#"
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properties:
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"#dma-cells":
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const: 5
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compatible:
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const: st,stm32h7-mdma
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reg:
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maxItems: 1
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clocks:
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maxItems: 1
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interrupts:
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maxItems: 1
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resets:
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maxItems: 1
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st,ahb-addr-masks:
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$ref: /schemas/types.yaml#/definitions/uint32-array
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description: Array of u32 mask to list memory devices addressed via AHB bus.
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required:
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- compatible
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- reg
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- clocks
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- interrupts
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unevaluatedProperties: false
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examples:
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- |
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#include <dt-bindings/interrupt-controller/arm-gic.h>
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#include <dt-bindings/clock/stm32mp1-clks.h>
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#include <dt-bindings/reset/stm32mp1-resets.h>
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dma-controller@52000000 {
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compatible = "st,stm32h7-mdma";
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reg = <0x52000000 0x1000>;
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interrupts = <122>;
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clocks = <&timer_clk>;
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resets = <&rcc 992>;
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#dma-cells = <5>;
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dma-channels = <16>;
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dma-requests = <32>;
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st,ahb-addr-masks = <0x20000000>, <0x00000000>;
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};
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...
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