100 lines
2.1 KiB
YAML
100 lines
2.1 KiB
YAML
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
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%YAML 1.2
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---
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$id: http://devicetree.org/schemas/dma/qcom,adm.yaml#
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$schema: http://devicetree.org/meta-schemas/core.yaml#
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title: Qualcomm ADM DMA Controller
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maintainers:
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- Christian Marangi <ansuelsmth@gmail.com>
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- Bjorn Andersson <bjorn.andersson@linaro.org>
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description: |
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QCOM ADM DMA controller provides DMA capabilities for
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peripheral buses such as NAND and SPI.
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properties:
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compatible:
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const: qcom,adm
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reg:
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maxItems: 1
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interrupts:
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maxItems: 1
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"#dma-cells":
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const: 1
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clocks:
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items:
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- description: phandle to the core clock
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- description: phandle to the iface clock
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clock-names:
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items:
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- const: core
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- const: iface
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resets:
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items:
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- description: phandle to the clk reset
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- description: phandle to the pbus reset
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- description: phandle to the c0 reset
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- description: phandle to the c1 reset
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- description: phandle to the c2 reset
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reset-names:
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items:
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- const: clk
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- const: pbus
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- const: c0
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- const: c1
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- const: c2
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qcom,ee:
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$ref: /schemas/types.yaml#/definitions/uint32
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description: indicates the security domain identifier used in the secure world.
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minimum: 0
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maximum: 255
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required:
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- compatible
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- reg
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- interrupts
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- "#dma-cells"
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- clocks
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- clock-names
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- resets
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- reset-names
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- qcom,ee
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additionalProperties: false
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examples:
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- |
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#include <dt-bindings/clock/qcom,gcc-ipq806x.h>
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#include <dt-bindings/reset/qcom,gcc-ipq806x.h>
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adm_dma: dma-controller@18300000 {
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compatible = "qcom,adm";
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reg = <0x18300000 0x100000>;
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interrupts = <0 170 0>;
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#dma-cells = <1>;
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clocks = <&gcc ADM0_CLK>,
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<&gcc ADM0_PBUS_CLK>;
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clock-names = "core", "iface";
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resets = <&gcc ADM0_RESET>,
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<&gcc ADM0_PBUS_RESET>,
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<&gcc ADM0_C0_RESET>,
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<&gcc ADM0_C1_RESET>,
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<&gcc ADM0_C2_RESET>;
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reset-names = "clk", "pbus", "c0", "c1", "c2";
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qcom,ee = <0>;
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};
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...
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