101 lines
2.3 KiB
Plaintext
101 lines
2.3 KiB
Plaintext
Texas Instruments OMAP5 Display Subsystem
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=========================================
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See Documentation/devicetree/bindings/display/ti/ti,omap-dss.txt for generic
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description about OMAP Display Subsystem bindings.
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DSS Core
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--------
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Required properties:
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- compatible: "ti,omap5-dss"
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- reg: address and length of the register space
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- ti,hwmods: "dss_core"
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- clocks: handle to fclk
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- clock-names: "fck"
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Required nodes:
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- DISPC
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Optional nodes:
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- DSS Submodules: RFBI, DSI, HDMI
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- Video port for DPI output
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DPI Endpoint required properties:
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- data-lines: number of lines used
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DISPC
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-----
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Required properties:
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- compatible: "ti,omap5-dispc"
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- reg: address and length of the register space
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- ti,hwmods: "dss_dispc"
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- interrupts: the DISPC interrupt
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- clocks: handle to fclk
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- clock-names: "fck"
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Optional properties:
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- max-memory-bandwidth: Input memory (from main memory to dispc) bandwidth limit
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in bytes per second
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RFBI
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----
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Required properties:
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- compatible: "ti,omap5-rfbi"
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- reg: address and length of the register space
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- ti,hwmods: "dss_rfbi"
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- clocks: handles to fclk and iclk
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- clock-names: "fck", "ick"
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Optional nodes:
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- Video port for RFBI output
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- RFBI controlled peripherals
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DSI
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---
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Required properties:
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- compatible: "ti,omap5-dsi"
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- reg: addresses and lengths of the register spaces for 'proto', 'phy' and 'pll'
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- reg-names: "proto", "phy", "pll"
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- interrupts: the DSI interrupt line
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- ti,hwmods: "dss_dsi1" or "dss_dsi2"
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- vdd-supply: power supply for DSI
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- clocks: handles to fclk and pll clock
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- clock-names: "fck", "sys_clk"
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Optional nodes:
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- Video port for DSI output
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- DSI controlled peripherals
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DSI Endpoint required properties:
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- lanes: list of pin numbers for the DSI lanes: CLK+, CLK-, DATA0+, DATA0-,
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DATA1+, DATA1-, ...
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HDMI
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----
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Required properties:
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- compatible: "ti,omap5-hdmi"
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- reg: addresses and lengths of the register spaces for 'wp', 'pll', 'phy',
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'core'
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- reg-names: "wp", "pll", "phy", "core"
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- interrupts: the HDMI interrupt line
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- ti,hwmods: "dss_hdmi"
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- vdda-supply: vdda power supply
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- clocks: handles to fclk and pll clock
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- clock-names: "fck", "sys_clk"
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Optional nodes:
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- Video port for HDMI output
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HDMI Endpoint optional properties:
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- lanes: list of 8 pin numbers for the HDMI lanes: CLK+, CLK-, D0+, D0-,
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D1+, D1-, D2+, D2-. (default: 0,1,2,3,4,5,6,7)
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