55 lines
1.2 KiB
Plaintext
55 lines
1.2 KiB
Plaintext
* TI - MPU (Main Processor Unit) subsystem
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The MPU subsystem contain one or several ARM cores
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depending of the version.
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The MPU contain CPUs, GIC, L2 cache and a local PRCM.
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Required properties:
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- compatible : Should be "ti,omap3-mpu" for OMAP3
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Should be "ti,omap4-mpu" for OMAP4
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Should be "ti,omap5-mpu" for OMAP5
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- ti,hwmods: "mpu"
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Optional properties:
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- sram: Phandle to the ocmcram node
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am335x and am437x only:
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- pm-sram: Phandles to ocmcram nodes to be used for power management.
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First should be type 'protect-exec' for the driver to use to copy
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and run PM functions, second should be regular pool to be used for
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data region for code. See Documentation/devicetree/bindings/sram/sram.yaml
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for more details.
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Examples:
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- For an OMAP5 SMP system:
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mpu {
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compatible = "ti,omap5-mpu";
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ti,hwmods = "mpu"
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};
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- For an OMAP4 SMP system:
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mpu {
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compatible = "ti,omap4-mpu";
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ti,hwmods = "mpu";
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};
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- For an OMAP3 monocore system:
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mpu {
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compatible = "ti,omap3-mpu";
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ti,hwmods = "mpu";
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};
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- For an AM335x system:
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mpu {
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compatible = "ti,omap3-mpu";
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ti,hwmods = "mpu";
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pm-sram = <&pm_sram_code
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&pm_sram_data>;
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};
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