731 lines
17 KiB
C
731 lines
17 KiB
C
/* SPDX-License-Identifier: GPL-2.0 */
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#ifndef __AUDIOREACH_H__
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#define __AUDIOREACH_H__
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#include <linux/types.h>
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#include <linux/soc/qcom/apr.h>
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#include <sound/soc.h>
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struct q6apm;
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struct q6apm_graph;
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/* Module IDs */
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#define MODULE_ID_WR_SHARED_MEM_EP 0x07001000
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#define MODULE_ID_RD_SHARED_MEM_EP 0x07001001
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#define MODULE_ID_GAIN 0x07001002
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#define MODULE_ID_PCM_CNV 0x07001003
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#define MODULE_ID_PCM_ENC 0x07001004
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#define MODULE_ID_PCM_DEC 0x07001005
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#define MODULE_ID_CODEC_DMA_SINK 0x07001023
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#define MODULE_ID_CODEC_DMA_SOURCE 0x07001024
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#define MODULE_ID_I2S_SINK 0x0700100A
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#define MODULE_ID_I2S_SOURCE 0x0700100B
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#define MODULE_ID_DATA_LOGGING 0x0700101A
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#define APM_CMD_GET_SPF_STATE 0x01001021
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#define APM_CMD_RSP_GET_SPF_STATE 0x02001007
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#define APM_MODULE_INSTANCE_ID 0x00000001
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#define PRM_MODULE_INSTANCE_ID 0x00000002
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#define AMDB_MODULE_INSTANCE_ID 0x00000003
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#define VCPM_MODULE_INSTANCE_ID 0x00000004
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#define AR_MODULE_INSTANCE_ID_START 0x00006000
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#define AR_MODULE_INSTANCE_ID_END 0x00007000
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#define AR_MODULE_DYNAMIC_INSTANCE_ID_START 0x00007000
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#define AR_MODULE_DYNAMIC_INSTANCE_ID_END 0x00008000
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#define AR_CONT_INSTANCE_ID_START 0x00005000
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#define AR_CONT_INSTANCE_ID_END 0x00006000
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#define AR_SG_INSTANCE_ID_START 0x00004000
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#define APM_CMD_GRAPH_OPEN 0x01001000
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#define APM_CMD_GRAPH_PREPARE 0x01001001
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#define APM_CMD_GRAPH_START 0x01001002
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#define APM_CMD_GRAPH_STOP 0x01001003
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#define APM_CMD_GRAPH_CLOSE 0x01001004
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#define APM_CMD_GRAPH_FLUSH 0x01001005
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#define APM_CMD_SET_CFG 0x01001006
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#define APM_CMD_GET_CFG 0x01001007
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#define APM_CMD_SHARED_MEM_MAP_REGIONS 0x0100100C
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#define APM_CMD_SHARED_MEM_UNMAP_REGIONS 0x0100100D
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#define APM_CMD_RSP_SHARED_MEM_MAP_REGIONS 0x02001001
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#define APM_CMD_RSP_GET_CFG 0x02001000
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#define APM_CMD_CLOSE_ALL 0x01001013
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#define APM_CMD_REGISTER_SHARED_CFG 0x0100100A
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#define APM_MEMORY_MAP_SHMEM8_4K_POOL 3
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struct apm_cmd_shared_mem_map_regions {
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uint16_t mem_pool_id;
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uint16_t num_regions;
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uint32_t property_flag;
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} __packed;
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struct apm_shared_map_region_payload {
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uint32_t shm_addr_lsw;
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uint32_t shm_addr_msw;
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uint32_t mem_size_bytes;
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} __packed;
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struct apm_cmd_shared_mem_unmap_regions {
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uint32_t mem_map_handle;
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} __packed;
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struct apm_cmd_rsp_shared_mem_map_regions {
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uint32_t mem_map_handle;
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} __packed;
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/* APM module */
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#define APM_PARAM_ID_SUB_GRAPH_LIST 0x08001005
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#define APM_PARAM_ID_MODULE_LIST 0x08001002
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struct apm_param_id_modules_list {
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uint32_t num_modules_list;
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} __packed;
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#define APM_PARAM_ID_MODULE_PROP 0x08001003
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struct apm_param_id_module_prop {
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uint32_t num_modules_prop_cfg;
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} __packed;
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struct apm_module_prop_cfg {
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uint32_t instance_id;
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uint32_t num_props;
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} __packed;
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#define APM_PARAM_ID_MODULE_CONN 0x08001004
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struct apm_param_id_module_conn {
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uint32_t num_connections;
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} __packed;
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struct apm_module_conn_obj {
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uint32_t src_mod_inst_id;
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uint32_t src_mod_op_port_id;
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uint32_t dst_mod_inst_id;
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uint32_t dst_mod_ip_port_id;
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} __packed;
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#define APM_PARAM_ID_GAIN 0x08001006
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struct param_id_gain_cfg {
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uint16_t gain;
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uint16_t reserved;
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} __packed;
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#define PARAM_ID_PCM_OUTPUT_FORMAT_CFG 0x08001008
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struct param_id_pcm_output_format_cfg {
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uint32_t data_format;
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uint32_t fmt_id;
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uint32_t payload_size;
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} __packed;
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struct payload_pcm_output_format_cfg {
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uint16_t bit_width;
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uint16_t alignment;
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uint16_t bits_per_sample;
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uint16_t q_factor;
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uint16_t endianness;
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uint16_t interleaved;
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uint16_t reserved;
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uint16_t num_channels;
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uint8_t channel_mapping[];
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} __packed;
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#define PARAM_ID_ENC_BITRATE 0x08001052
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struct param_id_enc_bitrate_param {
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uint32_t bitrate;
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} __packed;
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#define DATA_FORMAT_FIXED_POINT 1
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#define PCM_LSB_ALIGNED 1
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#define PCM_MSB_ALIGNED 2
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#define PCM_LITTLE_ENDIAN 1
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#define PCM_BIT_ENDIAN 2
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#define MEDIA_FMT_ID_PCM 0x09001000
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#define PCM_CHANNEL_L 1
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#define PCM_CHANNEL_R 2
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#define SAMPLE_RATE_48K 48000
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#define BIT_WIDTH_16 16
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#define APM_PARAM_ID_PROP_PORT_INFO 0x08001015
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struct apm_modules_prop_info {
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uint32_t max_ip_port;
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uint32_t max_op_port;
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} __packed;
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/* Shared memory module */
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#define DATA_CMD_WR_SH_MEM_EP_DATA_BUFFER 0x04001000
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#define WR_SH_MEM_EP_TIMESTAMP_VALID_FLAG BIT(31)
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#define WR_SH_MEM_EP_LAST_BUFFER_FLAG BIT(30)
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#define WR_SH_MEM_EP_TS_CONTINUE_FLAG BIT(29)
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#define WR_SH_MEM_EP_EOF_FLAG BIT(4)
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struct apm_data_cmd_wr_sh_mem_ep_data_buffer {
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uint32_t buf_addr_lsw;
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uint32_t buf_addr_msw;
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uint32_t mem_map_handle;
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uint32_t buf_size;
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uint32_t timestamp_lsw;
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uint32_t timestamp_msw;
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uint32_t flags;
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} __packed;
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#define DATA_CMD_WR_SH_MEM_EP_DATA_BUFFER_V2 0x0400100A
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struct apm_data_cmd_wr_sh_mem_ep_data_buffer_v2 {
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uint32_t buf_addr_lsw;
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uint32_t buf_addr_msw;
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uint32_t mem_map_handle;
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uint32_t buf_size;
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uint32_t timestamp_lsw;
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uint32_t timestamp_msw;
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uint32_t flags;
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uint32_t md_addr_lsw;
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uint32_t md_addr_msw;
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uint32_t md_map_handle;
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uint32_t md_buf_size;
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} __packed;
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#define DATA_CMD_RSP_WR_SH_MEM_EP_DATA_BUFFER_DONE 0x05001000
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struct data_cmd_rsp_wr_sh_mem_ep_data_buffer_done {
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uint32_t buf_addr_lsw;
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uint32_t buf_addr_msw;
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uint32_t mem_map_handle;
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uint32_t status;
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} __packed;
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#define DATA_CMD_RSP_WR_SH_MEM_EP_DATA_BUFFER_DONE_V2 0x05001004
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struct data_cmd_rsp_wr_sh_mem_ep_data_buffer_done_v2 {
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uint32_t buf_addr_lsw;
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uint32_t buf_addr_msw;
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uint32_t mem_map_handle;
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uint32_t status;
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uint32_t md_buf_addr_lsw;
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uint32_t md_buf_addr_msw;
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uint32_t md_mem_map_handle;
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uint32_t md_status;
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} __packed;
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#define PARAM_ID_MEDIA_FORMAT 0x0800100C
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#define DATA_CMD_WR_SH_MEM_EP_MEDIA_FORMAT 0x04001001
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struct apm_media_format {
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uint32_t data_format;
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uint32_t fmt_id;
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uint32_t payload_size;
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} __packed;
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#define DATA_CMD_WR_SH_MEM_EP_EOS 0x04001002
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#define WR_SH_MEM_EP_EOS_POLICY_LAST 1
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#define WR_SH_MEM_EP_EOS_POLICY_EACH 2
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struct data_cmd_wr_sh_mem_ep_eos {
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uint32_t policy;
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} __packed;
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#define DATA_CMD_RD_SH_MEM_EP_DATA_BUFFER 0x04001003
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struct data_cmd_rd_sh_mem_ep_data_buffer {
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uint32_t buf_addr_lsw;
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uint32_t buf_addr_msw;
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uint32_t mem_map_handle;
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uint32_t buf_size;
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} __packed;
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#define DATA_CMD_RSP_RD_SH_MEM_EP_DATA_BUFFER 0x05001002
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struct data_cmd_rsp_rd_sh_mem_ep_data_buffer_done {
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uint32_t status;
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uint32_t buf_addr_lsw;
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uint32_t buf_addr_msw;
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uint32_t mem_map_handle;
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uint32_t data_size;
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uint32_t offset;
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uint32_t timestamp_lsw;
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uint32_t timestamp_msw;
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uint32_t flags;
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uint32_t num_frames;
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} __packed;
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#define DATA_CMD_RD_SH_MEM_EP_DATA_BUFFER_V2 0x0400100B
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struct data_cmd_rd_sh_mem_ep_data_buffer_v2 {
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uint32_t buf_addr_lsw;
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uint32_t buf_addr_msw;
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uint32_t mem_map_handle;
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uint32_t buf_size;
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uint32_t md_buf_addr_lsw;
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uint32_t md_buf_addr_msw;
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uint32_t md_mem_map_handle;
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uint32_t md_buf_size;
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} __packed;
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#define DATA_CMD_RSP_RD_SH_MEM_EP_DATA_BUFFER_V2 0x05001005
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struct data_cmd_rsp_rd_sh_mem_ep_data_buffer_done_v2 {
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uint32_t status;
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uint32_t buf_addr_lsw;
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uint32_t buf_addr_msw;
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uint32_t mem_map_handle;
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uint32_t data_size;
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uint32_t offset;
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uint32_t timestamp_lsw;
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uint32_t timestamp_msw;
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uint32_t flags;
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uint32_t num_frames;
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uint32_t md_status;
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uint32_t md_buf_addr_lsw;
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uint32_t md_buf_addr_msw;
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uint32_t md_mem_map_handle;
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uint32_t md_size;
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} __packed;
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#define PARAM_ID_RD_SH_MEM_CFG 0x08001007
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struct param_id_rd_sh_mem_cfg {
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uint32_t num_frames_per_buffer;
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uint32_t metadata_control_flags;
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} __packed;
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#define DATA_CMD_WR_SH_MEM_EP_EOS_RENDERED 0x05001001
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struct data_cmd_wr_sh_mem_ep_eos_rendered {
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uint32_t module_instance_id;
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uint32_t render_status;
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} __packed;
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#define MODULE_ID_WR_SHARED_MEM_EP 0x07001000
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struct apm_cmd_header {
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uint32_t payload_address_lsw;
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uint32_t payload_address_msw;
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uint32_t mem_map_handle;
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uint32_t payload_size;
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} __packed;
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#define APM_CMD_HDR_SIZE sizeof(struct apm_cmd_header)
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struct apm_module_param_data {
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uint32_t module_instance_id;
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uint32_t param_id;
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uint32_t param_size;
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uint32_t error_code;
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} __packed;
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#define APM_MODULE_PARAM_DATA_SIZE sizeof(struct apm_module_param_data)
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struct apm_module_param_shared_data {
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uint32_t param_id;
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uint32_t param_size;
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} __packed;
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struct apm_prop_data {
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uint32_t prop_id;
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uint32_t prop_size;
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} __packed;
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/* Sub-Graph Properties */
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#define APM_PARAM_ID_SUB_GRAPH_CONFIG 0x08001001
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struct apm_param_id_sub_graph_cfg {
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uint32_t num_sub_graphs;
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} __packed;
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struct apm_sub_graph_cfg {
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uint32_t sub_graph_id;
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uint32_t num_sub_graph_prop;
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} __packed;
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#define APM_SUB_GRAPH_PROP_ID_PERF_MODE 0x0800100E
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struct apm_sg_prop_id_perf_mode {
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uint32_t perf_mode;
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} __packed;
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#define APM_SG_PROP_ID_PERF_MODE_SIZE 4
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#define APM_SUB_GRAPH_PROP_ID_DIRECTION 0x0800100F
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struct apm_sg_prop_id_direction {
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uint32_t direction;
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} __packed;
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#define APM_SG_PROP_ID_DIR_SIZE 4
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#define APM_SUB_GRAPH_PROP_ID_SCENARIO_ID 0x08001010
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#define APM_SUB_GRAPH_SID_AUDIO_PLAYBACK 0x1
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#define APM_SUB_GRAPH_SID_AUDIO_RECORD 0x2
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#define APM_SUB_GRAPH_SID_AUDIO_VOICE_CALL 0x3
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struct apm_sg_prop_id_scenario_id {
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uint32_t scenario_id;
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} __packed;
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#define APM_SG_PROP_ID_SID_SIZE 4
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/* container api */
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#define APM_PARAM_ID_CONTAINER_CONFIG 0x08001000
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struct apm_param_id_container_cfg {
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uint32_t num_containers;
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} __packed;
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struct apm_container_cfg {
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uint32_t container_id;
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uint32_t num_prop;
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} __packed;
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struct apm_cont_capability {
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uint32_t capability_id;
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} __packed;
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#define APM_CONTAINER_PROP_ID_CAPABILITY_LIST 0x08001011
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#define APM_CONTAINER_PROP_ID_CAPABILITY_SIZE 8
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#define APM_PROP_ID_INVALID 0x0
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#define APM_CONTAINER_CAP_ID_PP 0x1
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#define APM_CONTAINER_CAP_ID_PP 0x1
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struct apm_cont_prop_id_cap_list {
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uint32_t num_capability_id;
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} __packed;
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#define APM_CONTAINER_PROP_ID_GRAPH_POS 0x08001012
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struct apm_cont_prop_id_graph_pos {
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uint32_t graph_pos;
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} __packed;
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#define APM_CONTAINER_PROP_ID_STACK_SIZE 0x08001013
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struct apm_cont_prop_id_stack_size {
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uint32_t stack_size;
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} __packed;
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#define APM_CONTAINER_PROP_ID_PROC_DOMAIN 0x08001014
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struct apm_cont_prop_id_domain {
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uint32_t proc_domain;
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} __packed;
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#define CONFIG_I2S_WS_SRC_EXTERNAL 0x0
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#define CONFIG_I2S_WS_SRC_INTERNAL 0x1
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#define PARAM_ID_I2S_INTF_CFG 0x08001019
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struct param_id_i2s_intf_cfg {
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uint32_t lpaif_type;
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uint32_t intf_idx;
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uint16_t sd_line_idx;
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uint16_t ws_src;
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} __packed;
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#define I2S_INTF_TYPE_PRIMARY 0
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#define I2S_INTF_TYPE_SECOINDARY 1
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#define I2S_INTF_TYPE_TERTINARY 2
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#define I2S_INTF_TYPE_QUATERNARY 3
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#define I2S_INTF_TYPE_QUINARY 4
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#define I2S_SD0 1
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#define I2S_SD1 2
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#define I2S_SD2 3
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#define I2S_SD3 4
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#define PORT_ID_I2S_INPUT 2
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#define PORT_ID_I2S_OUPUT 1
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#define I2S_STACK_SIZE 2048
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#define PARAM_ID_HW_EP_MF_CFG 0x08001017
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struct param_id_hw_ep_mf {
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uint32_t sample_rate;
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uint16_t bit_width;
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uint16_t num_channels;
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uint32_t data_format;
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} __packed;
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#define PARAM_ID_HW_EP_FRAME_SIZE_FACTOR 0x08001018
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struct param_id_fram_size_factor {
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uint32_t frame_size_factor;
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} __packed;
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#define APM_CONTAINER_PROP_ID_PARENT_CONTAINER_ID 0x080010CB
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struct apm_cont_prop_id_parent_container {
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uint32_t parent_container_id;
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} __packed;
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#define APM_CONTAINER_PROP_ID_HEAP_ID 0x08001174
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#define APM_CONT_HEAP_DEFAULT 0x1
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#define APM_CONT_HEAP_LOW_POWER 0x2
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struct apm_cont_prop_id_headp_id {
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uint32_t heap_id;
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} __packed;
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struct apm_modules_list {
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uint32_t sub_graph_id;
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uint32_t container_id;
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uint32_t num_modules;
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} __packed;
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struct apm_module_obj {
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uint32_t module_id;
|
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uint32_t instance_id;
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} __packed;
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#define APM_MODULE_PROP_ID_PORT_INFO 0x08001015
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#define APM_MODULE_PROP_ID_PORT_INFO_SZ 8
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struct apm_module_prop_id_port_info {
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uint32_t max_ip_port;
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uint32_t max_op_port;
|
|
} __packed;
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#define DATA_LOGGING_MAX_INPUT_PORTS 0x1
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#define DATA_LOGGING_MAX_OUTPUT_PORTS 0x1
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#define DATA_LOGGING_STACK_SIZE 2048
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#define PARAM_ID_DATA_LOGGING_CONFIG 0x08001031
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struct data_logging_config {
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uint32_t log_code;
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uint32_t log_tap_point_id;
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uint32_t mode;
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} __packed;
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#define PARAM_ID_MFC_OUTPUT_MEDIA_FORMAT 0x08001024
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struct param_id_mfc_media_format {
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uint32_t sample_rate;
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uint16_t bit_width;
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uint16_t num_channels;
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uint16_t channel_mapping[];
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} __packed;
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struct media_format {
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uint32_t data_format;
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uint32_t fmt_id;
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uint32_t payload_size;
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} __packed;
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struct payload_media_fmt_pcm {
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uint32_t sample_rate;
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uint16_t bit_width;
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uint16_t alignment;
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uint16_t bits_per_sample;
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uint16_t q_factor;
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uint16_t endianness;
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uint16_t num_channels;
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uint8_t channel_mapping[];
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} __packed;
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#define PARAM_ID_CODEC_DMA_INTF_CFG 0x08001063
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struct param_id_codec_dma_intf_cfg {
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/* 1 - RXTX
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* 2 - WSA
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* 3 - VA
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* 4 - AXI
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*/
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uint32_t lpaif_type;
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/*
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* RX0 | TX0 = 1
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* RX1 | TX1 = 2
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* RX2 | TX2 = 3... so on
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*/
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uint32_t intf_index;
|
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uint32_t active_channels_mask;
|
|
} __packed;
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|
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struct audio_hw_clk_cfg {
|
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uint32_t clock_id;
|
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uint32_t clock_freq;
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uint32_t clock_attri;
|
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uint32_t clock_root;
|
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} __packed;
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|
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struct audio_hw_clk_rel_cfg {
|
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uint32_t clock_id;
|
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} __packed;
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|
|
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#define PARAM_ID_HW_EP_POWER_MODE_CFG 0x8001176
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#define AR_HW_EP_POWER_MODE_0 0 /* default */
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#define AR_HW_EP_POWER_MODE_1 1 /* XO Shutdown allowed */
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#define AR_HW_EP_POWER_MODE_2 2 /* XO Shutdown not allowed */
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|
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struct param_id_hw_ep_power_mode_cfg {
|
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uint32_t power_mode;
|
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} __packed;
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#define PARAM_ID_HW_EP_DMA_DATA_ALIGN 0x08001233
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#define AR_HW_EP_DMA_DATA_ALIGN_MSB 0
|
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#define AR_HW_EP_DMA_DATA_ALIGN_LSB 1
|
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#define AR_PCM_MAX_NUM_CHANNEL 8
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|
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struct param_id_hw_ep_dma_data_align {
|
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uint32_t dma_data_align;
|
|
} __packed;
|
|
|
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#define PARAM_ID_VOL_CTRL_MASTER_GAIN 0x08001035
|
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#define VOL_CTRL_DEFAULT_GAIN 0x2000
|
|
|
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struct param_id_vol_ctrl_master_gain {
|
|
uint16_t master_gain;
|
|
uint16_t reserved;
|
|
} __packed;
|
|
|
|
|
|
/* Graph */
|
|
struct audioreach_connection {
|
|
/* Connections */
|
|
uint32_t src_mod_inst_id;
|
|
uint32_t src_mod_op_port_id;
|
|
uint32_t dst_mod_inst_id;
|
|
uint32_t dst_mod_ip_port_id;
|
|
struct list_head node;
|
|
};
|
|
|
|
struct audioreach_graph_info {
|
|
int id;
|
|
uint32_t num_sub_graphs;
|
|
struct list_head sg_list;
|
|
struct list_head connection_list;
|
|
};
|
|
|
|
struct audioreach_sub_graph {
|
|
uint32_t sub_graph_id;
|
|
uint32_t perf_mode;
|
|
uint32_t direction;
|
|
uint32_t scenario_id;
|
|
struct list_head node;
|
|
|
|
struct audioreach_graph_info *info;
|
|
uint32_t num_containers;
|
|
struct list_head container_list;
|
|
};
|
|
|
|
struct audioreach_container {
|
|
uint32_t container_id;
|
|
uint32_t capability_id;
|
|
uint32_t graph_pos;
|
|
uint32_t stack_size;
|
|
uint32_t proc_domain;
|
|
struct list_head node;
|
|
|
|
uint32_t num_modules;
|
|
struct list_head modules_list;
|
|
struct audioreach_sub_graph *sub_graph;
|
|
};
|
|
|
|
struct audioreach_module {
|
|
uint32_t module_id;
|
|
uint32_t instance_id;
|
|
|
|
uint32_t max_ip_port;
|
|
uint32_t max_op_port;
|
|
|
|
uint32_t in_port;
|
|
uint32_t out_port;
|
|
|
|
/* Connections */
|
|
uint32_t src_mod_inst_id;
|
|
uint32_t src_mod_op_port_id;
|
|
uint32_t dst_mod_inst_id;
|
|
uint32_t dst_mod_ip_port_id;
|
|
|
|
/* Format specifics */
|
|
uint32_t ch_fmt;
|
|
uint32_t rate;
|
|
uint32_t bit_depth;
|
|
|
|
/* I2S module */
|
|
uint32_t hw_interface_idx;
|
|
uint32_t sd_line_idx;
|
|
uint32_t ws_src;
|
|
uint32_t frame_size_factor;
|
|
uint32_t data_format;
|
|
uint32_t hw_interface_type;
|
|
|
|
/* PCM module specific */
|
|
uint32_t interleave_type;
|
|
|
|
/* GAIN/Vol Control Module */
|
|
uint16_t gain;
|
|
|
|
/* Logging */
|
|
uint32_t log_code;
|
|
uint32_t log_tap_point_id;
|
|
uint32_t log_mode;
|
|
|
|
/* bookkeeping */
|
|
struct list_head node;
|
|
struct audioreach_container *container;
|
|
struct snd_soc_dapm_widget *widget;
|
|
};
|
|
|
|
struct audioreach_module_config {
|
|
int direction;
|
|
u32 sample_rate;
|
|
u16 bit_width;
|
|
u16 bits_per_sample;
|
|
|
|
u16 data_format;
|
|
u16 num_channels;
|
|
u16 active_channels_mask;
|
|
u32 sd_line_mask;
|
|
int fmt;
|
|
u8 channel_map[AR_PCM_MAX_NUM_CHANNEL];
|
|
};
|
|
|
|
/* Packet Allocation routines */
|
|
void *audioreach_alloc_apm_cmd_pkt(int pkt_size, uint32_t opcode, uint32_t
|
|
token);
|
|
void *audioreach_alloc_cmd_pkt(int payload_size, uint32_t opcode,
|
|
uint32_t token, uint32_t src_port,
|
|
uint32_t dest_port);
|
|
void *audioreach_alloc_apm_pkt(int pkt_size, uint32_t opcode, uint32_t token,
|
|
uint32_t src_port);
|
|
void *audioreach_alloc_pkt(int payload_size, uint32_t opcode,
|
|
uint32_t token, uint32_t src_port,
|
|
uint32_t dest_port);
|
|
void *audioreach_alloc_graph_pkt(struct q6apm *apm,
|
|
struct list_head *sg_list,
|
|
int graph_id);
|
|
/* Topology specific */
|
|
int audioreach_tplg_init(struct snd_soc_component *component);
|
|
|
|
/* Module specific */
|
|
void audioreach_graph_free_buf(struct q6apm_graph *graph);
|
|
int audioreach_map_memory_regions(struct q6apm_graph *graph,
|
|
unsigned int dir, size_t period_sz,
|
|
unsigned int periods,
|
|
bool is_contiguous);
|
|
int audioreach_send_cmd_sync(struct device *dev, gpr_device_t *gdev, struct gpr_ibasic_rsp_result_t *result,
|
|
struct mutex *cmd_lock, gpr_port_t *port, wait_queue_head_t *cmd_wait,
|
|
struct gpr_pkt *pkt, uint32_t rsp_opcode);
|
|
int audioreach_graph_send_cmd_sync(struct q6apm_graph *graph, struct gpr_pkt *pkt,
|
|
uint32_t rsp_opcode);
|
|
int audioreach_set_media_format(struct q6apm_graph *graph,
|
|
struct audioreach_module *module,
|
|
struct audioreach_module_config *cfg);
|
|
int audioreach_shared_memory_send_eos(struct q6apm_graph *graph);
|
|
int audioreach_gain_set_vol_ctrl(struct q6apm *apm,
|
|
struct audioreach_module *module, int vol);
|
|
struct audioreach_module *audioreach_get_container_last_module(
|
|
struct audioreach_container *container);
|
|
struct audioreach_module *audioreach_get_container_first_module(
|
|
struct audioreach_container *container);
|
|
struct audioreach_module *audioreach_get_container_next_module(
|
|
struct audioreach_container *container,
|
|
struct audioreach_module *module);
|
|
#define list_for_each_container_module(mod, cont) \
|
|
for (mod = audioreach_get_container_first_module(cont); mod != NULL; \
|
|
mod = audioreach_get_container_next_module(cont, mod))
|
|
#endif /* __AUDIOREACH_H__ */
|