509 lines
19 KiB
C
509 lines
19 KiB
C
/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */
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/*
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* Copyright (c) 2021, The Linux Foundation. All rights reserved.
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* Copyright (c) 2022, Linaro Ltd.
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*/
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#ifndef _DT_BINDINGS_CLK_QCOM_GCC_DIREWOLF_H
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#define _DT_BINDINGS_CLK_QCOM_GCC_DIREWOLF_H
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/* GCC clocks */
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#define GCC_GPLL0 0
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#define GCC_GPLL0_OUT_EVEN 1
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#define GCC_GPLL2 2
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#define GCC_GPLL4 3
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#define GCC_GPLL7 4
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#define GCC_GPLL8 5
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#define GCC_GPLL9 6
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#define GCC_AGGRE_NOC_PCIE0_TUNNEL_AXI_CLK 7
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#define GCC_AGGRE_NOC_PCIE1_TUNNEL_AXI_CLK 8
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#define GCC_AGGRE_NOC_PCIE_4_AXI_CLK 9
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#define GCC_AGGRE_NOC_PCIE_SOUTH_SF_AXI_CLK 10
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#define GCC_AGGRE_UFS_CARD_AXI_CLK 11
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#define GCC_AGGRE_UFS_PHY_AXI_CLK 12
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#define GCC_AGGRE_USB3_MP_AXI_CLK 13
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#define GCC_AGGRE_USB3_PRIM_AXI_CLK 14
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#define GCC_AGGRE_USB3_SEC_AXI_CLK 15
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#define GCC_AGGRE_USB4_1_AXI_CLK 16
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#define GCC_AGGRE_USB4_AXI_CLK 17
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#define GCC_AGGRE_USB_NOC_AXI_CLK 18
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#define GCC_AGGRE_USB_NOC_NORTH_AXI_CLK 19
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#define GCC_AGGRE_USB_NOC_SOUTH_AXI_CLK 20
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#define GCC_AHB2PHY0_CLK 21
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#define GCC_AHB2PHY2_CLK 22
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#define GCC_BOOT_ROM_AHB_CLK 23
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#define GCC_CAMERA_AHB_CLK 24
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#define GCC_CAMERA_HF_AXI_CLK 25
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#define GCC_CAMERA_SF_AXI_CLK 26
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#define GCC_CAMERA_THROTTLE_NRT_AXI_CLK 27
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#define GCC_CAMERA_THROTTLE_RT_AXI_CLK 28
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#define GCC_CAMERA_THROTTLE_XO_CLK 29
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#define GCC_CAMERA_XO_CLK 30
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#define GCC_CFG_NOC_USB3_MP_AXI_CLK 31
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#define GCC_CFG_NOC_USB3_PRIM_AXI_CLK 32
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#define GCC_CFG_NOC_USB3_SEC_AXI_CLK 33
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#define GCC_CNOC_PCIE0_TUNNEL_CLK 34
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#define GCC_CNOC_PCIE1_TUNNEL_CLK 35
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#define GCC_CNOC_PCIE4_QX_CLK 36
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#define GCC_DDRSS_GPU_AXI_CLK 37
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#define GCC_DDRSS_PCIE_SF_TBU_CLK 38
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#define GCC_DISP1_AHB_CLK 39
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#define GCC_DISP1_HF_AXI_CLK 40
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#define GCC_DISP1_SF_AXI_CLK 41
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#define GCC_DISP1_THROTTLE_NRT_AXI_CLK 42
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#define GCC_DISP1_THROTTLE_RT_AXI_CLK 43
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#define GCC_DISP1_XO_CLK 44
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#define GCC_DISP_AHB_CLK 45
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#define GCC_DISP_HF_AXI_CLK 46
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#define GCC_DISP_SF_AXI_CLK 47
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#define GCC_DISP_THROTTLE_NRT_AXI_CLK 48
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#define GCC_DISP_THROTTLE_RT_AXI_CLK 49
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#define GCC_DISP_XO_CLK 50
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#define GCC_EMAC0_AXI_CLK 51
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#define GCC_EMAC0_PTP_CLK 52
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#define GCC_EMAC0_PTP_CLK_SRC 53
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#define GCC_EMAC0_RGMII_CLK 54
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#define GCC_EMAC0_RGMII_CLK_SRC 55
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#define GCC_EMAC0_SLV_AHB_CLK 56
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#define GCC_EMAC1_AXI_CLK 57
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#define GCC_EMAC1_PTP_CLK 58
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#define GCC_EMAC1_PTP_CLK_SRC 59
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#define GCC_EMAC1_RGMII_CLK 60
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#define GCC_EMAC1_RGMII_CLK_SRC 61
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#define GCC_EMAC1_SLV_AHB_CLK 62
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#define GCC_GP1_CLK 63
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#define GCC_GP1_CLK_SRC 64
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#define GCC_GP2_CLK 65
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#define GCC_GP2_CLK_SRC 66
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#define GCC_GP3_CLK 67
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#define GCC_GP3_CLK_SRC 68
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#define GCC_GP4_CLK 69
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#define GCC_GP4_CLK_SRC 70
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#define GCC_GP5_CLK 71
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#define GCC_GP5_CLK_SRC 72
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#define GCC_GPU_CFG_AHB_CLK 73
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#define GCC_GPU_GPLL0_CLK_SRC 74
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#define GCC_GPU_GPLL0_DIV_CLK_SRC 75
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#define GCC_GPU_IREF_EN 76
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#define GCC_GPU_MEMNOC_GFX_CLK 77
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#define GCC_GPU_SNOC_DVM_GFX_CLK 78
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#define GCC_GPU_TCU_THROTTLE_AHB_CLK 79
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#define GCC_GPU_TCU_THROTTLE_CLK 80
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#define GCC_PCIE0_PHY_RCHNG_CLK 81
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#define GCC_PCIE1_PHY_RCHNG_CLK 82
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#define GCC_PCIE2A_PHY_RCHNG_CLK 83
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#define GCC_PCIE2B_PHY_RCHNG_CLK 84
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#define GCC_PCIE3A_PHY_RCHNG_CLK 85
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#define GCC_PCIE3B_PHY_RCHNG_CLK 86
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#define GCC_PCIE4_PHY_RCHNG_CLK 87
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#define GCC_PCIE_0_AUX_CLK 88
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#define GCC_PCIE_0_AUX_CLK_SRC 89
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#define GCC_PCIE_0_CFG_AHB_CLK 90
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#define GCC_PCIE_0_MSTR_AXI_CLK 91
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#define GCC_PCIE_0_PHY_RCHNG_CLK_SRC 92
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#define GCC_PCIE_0_PIPE_CLK 93
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#define GCC_PCIE_0_SLV_AXI_CLK 94
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#define GCC_PCIE_0_SLV_Q2A_AXI_CLK 95
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#define GCC_PCIE_1_AUX_CLK 96
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#define GCC_PCIE_1_AUX_CLK_SRC 97
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#define GCC_PCIE_1_CFG_AHB_CLK 98
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#define GCC_PCIE_1_MSTR_AXI_CLK 99
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#define GCC_PCIE_1_PHY_RCHNG_CLK_SRC 100
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#define GCC_PCIE_1_PIPE_CLK 101
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#define GCC_PCIE_1_SLV_AXI_CLK 102
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#define GCC_PCIE_1_SLV_Q2A_AXI_CLK 103
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#define GCC_PCIE_2A2B_CLKREF_CLK 104
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#define GCC_PCIE_2A_AUX_CLK 105
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#define GCC_PCIE_2A_AUX_CLK_SRC 106
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#define GCC_PCIE_2A_CFG_AHB_CLK 107
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#define GCC_PCIE_2A_MSTR_AXI_CLK 108
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#define GCC_PCIE_2A_PHY_RCHNG_CLK_SRC 109
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#define GCC_PCIE_2A_PIPE_CLK 110
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#define GCC_PCIE_2A_PIPE_CLK_SRC 111
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#define GCC_PCIE_2A_PIPE_DIV_CLK_SRC 112
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#define GCC_PCIE_2A_PIPEDIV2_CLK 113
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#define GCC_PCIE_2A_SLV_AXI_CLK 114
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#define GCC_PCIE_2A_SLV_Q2A_AXI_CLK 115
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#define GCC_PCIE_2B_AUX_CLK 116
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#define GCC_PCIE_2B_AUX_CLK_SRC 117
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#define GCC_PCIE_2B_CFG_AHB_CLK 118
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#define GCC_PCIE_2B_MSTR_AXI_CLK 119
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#define GCC_PCIE_2B_PHY_RCHNG_CLK_SRC 120
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#define GCC_PCIE_2B_PIPE_CLK 121
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#define GCC_PCIE_2B_PIPE_CLK_SRC 122
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#define GCC_PCIE_2B_PIPE_DIV_CLK_SRC 123
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#define GCC_PCIE_2B_PIPEDIV2_CLK 124
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#define GCC_PCIE_2B_SLV_AXI_CLK 125
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#define GCC_PCIE_2B_SLV_Q2A_AXI_CLK 126
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#define GCC_PCIE_3A3B_CLKREF_CLK 127
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#define GCC_PCIE_3A_AUX_CLK 128
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#define GCC_PCIE_3A_AUX_CLK_SRC 129
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#define GCC_PCIE_3A_CFG_AHB_CLK 130
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#define GCC_PCIE_3A_MSTR_AXI_CLK 131
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#define GCC_PCIE_3A_PHY_RCHNG_CLK_SRC 132
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#define GCC_PCIE_3A_PIPE_CLK 133
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#define GCC_PCIE_3A_PIPE_CLK_SRC 134
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#define GCC_PCIE_3A_PIPE_DIV_CLK_SRC 135
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#define GCC_PCIE_3A_PIPEDIV2_CLK 136
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#define GCC_PCIE_3A_SLV_AXI_CLK 137
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#define GCC_PCIE_3A_SLV_Q2A_AXI_CLK 138
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#define GCC_PCIE_3B_AUX_CLK 139
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#define GCC_PCIE_3B_AUX_CLK_SRC 140
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#define GCC_PCIE_3B_CFG_AHB_CLK 141
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#define GCC_PCIE_3B_MSTR_AXI_CLK 142
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#define GCC_PCIE_3B_PHY_RCHNG_CLK_SRC 143
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#define GCC_PCIE_3B_PIPE_CLK 144
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#define GCC_PCIE_3B_PIPE_CLK_SRC 145
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#define GCC_PCIE_3B_PIPE_DIV_CLK_SRC 146
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#define GCC_PCIE_3B_PIPEDIV2_CLK 147
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#define GCC_PCIE_3B_SLV_AXI_CLK 148
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#define GCC_PCIE_3B_SLV_Q2A_AXI_CLK 149
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#define GCC_PCIE_4_AUX_CLK 150
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#define GCC_PCIE_4_AUX_CLK_SRC 151
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#define GCC_PCIE_4_CFG_AHB_CLK 152
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#define GCC_PCIE_4_CLKREF_CLK 153
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#define GCC_PCIE_4_MSTR_AXI_CLK 154
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#define GCC_PCIE_4_PHY_RCHNG_CLK_SRC 155
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#define GCC_PCIE_4_PIPE_CLK 156
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#define GCC_PCIE_4_PIPE_CLK_SRC 157
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#define GCC_PCIE_4_PIPE_DIV_CLK_SRC 158
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#define GCC_PCIE_4_PIPEDIV2_CLK 159
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#define GCC_PCIE_4_SLV_AXI_CLK 160
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#define GCC_PCIE_4_SLV_Q2A_AXI_CLK 161
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#define GCC_PCIE_RSCC_AHB_CLK 162
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#define GCC_PCIE_RSCC_XO_CLK 163
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#define GCC_PCIE_RSCC_XO_CLK_SRC 164
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#define GCC_PCIE_THROTTLE_CFG_CLK 165
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#define GCC_PDM2_CLK 166
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#define GCC_PDM2_CLK_SRC 167
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#define GCC_PDM_AHB_CLK 168
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#define GCC_PDM_XO4_CLK 169
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#define GCC_QMIP_CAMERA_NRT_AHB_CLK 170
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#define GCC_QMIP_CAMERA_RT_AHB_CLK 171
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#define GCC_QMIP_DISP1_AHB_CLK 172
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#define GCC_QMIP_DISP1_ROT_AHB_CLK 173
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#define GCC_QMIP_DISP_AHB_CLK 174
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#define GCC_QMIP_DISP_ROT_AHB_CLK 175
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#define GCC_QMIP_VIDEO_CVP_AHB_CLK 176
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#define GCC_QMIP_VIDEO_VCODEC_AHB_CLK 177
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#define GCC_QUPV3_WRAP0_CORE_2X_CLK 178
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#define GCC_QUPV3_WRAP0_CORE_CLK 179
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#define GCC_QUPV3_WRAP0_QSPI0_CLK 180
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#define GCC_QUPV3_WRAP0_S0_CLK 181
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#define GCC_QUPV3_WRAP0_S0_CLK_SRC 182
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#define GCC_QUPV3_WRAP0_S1_CLK 183
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#define GCC_QUPV3_WRAP0_S1_CLK_SRC 184
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#define GCC_QUPV3_WRAP0_S2_CLK 185
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#define GCC_QUPV3_WRAP0_S2_CLK_SRC 186
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#define GCC_QUPV3_WRAP0_S3_CLK 187
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#define GCC_QUPV3_WRAP0_S3_CLK_SRC 188
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#define GCC_QUPV3_WRAP0_S4_CLK 189
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#define GCC_QUPV3_WRAP0_S4_CLK_SRC 190
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#define GCC_QUPV3_WRAP0_S4_DIV_CLK_SRC 191
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#define GCC_QUPV3_WRAP0_S5_CLK 192
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#define GCC_QUPV3_WRAP0_S5_CLK_SRC 193
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#define GCC_QUPV3_WRAP0_S6_CLK 194
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#define GCC_QUPV3_WRAP0_S6_CLK_SRC 195
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#define GCC_QUPV3_WRAP0_S7_CLK 196
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#define GCC_QUPV3_WRAP0_S7_CLK_SRC 197
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#define GCC_QUPV3_WRAP1_CORE_2X_CLK 198
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#define GCC_QUPV3_WRAP1_CORE_CLK 199
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#define GCC_QUPV3_WRAP1_QSPI0_CLK 200
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#define GCC_QUPV3_WRAP1_S0_CLK 201
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#define GCC_QUPV3_WRAP1_S0_CLK_SRC 202
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#define GCC_QUPV3_WRAP1_S1_CLK 203
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#define GCC_QUPV3_WRAP1_S1_CLK_SRC 204
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#define GCC_QUPV3_WRAP1_S2_CLK 205
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#define GCC_QUPV3_WRAP1_S2_CLK_SRC 206
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#define GCC_QUPV3_WRAP1_S3_CLK 207
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#define GCC_QUPV3_WRAP1_S3_CLK_SRC 208
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#define GCC_QUPV3_WRAP1_S4_CLK 209
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#define GCC_QUPV3_WRAP1_S4_CLK_SRC 210
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#define GCC_QUPV3_WRAP1_S4_DIV_CLK_SRC 211
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#define GCC_QUPV3_WRAP1_S5_CLK 212
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#define GCC_QUPV3_WRAP1_S5_CLK_SRC 213
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#define GCC_QUPV3_WRAP1_S6_CLK 214
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#define GCC_QUPV3_WRAP1_S6_CLK_SRC 215
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#define GCC_QUPV3_WRAP1_S7_CLK 216
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#define GCC_QUPV3_WRAP1_S7_CLK_SRC 217
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#define GCC_QUPV3_WRAP2_CORE_2X_CLK 218
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#define GCC_QUPV3_WRAP2_CORE_CLK 219
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#define GCC_QUPV3_WRAP2_QSPI0_CLK 220
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#define GCC_QUPV3_WRAP2_S0_CLK 221
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#define GCC_QUPV3_WRAP2_S0_CLK_SRC 222
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#define GCC_QUPV3_WRAP2_S1_CLK 223
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#define GCC_QUPV3_WRAP2_S1_CLK_SRC 224
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#define GCC_QUPV3_WRAP2_S2_CLK 225
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#define GCC_QUPV3_WRAP2_S2_CLK_SRC 226
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#define GCC_QUPV3_WRAP2_S3_CLK 227
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#define GCC_QUPV3_WRAP2_S3_CLK_SRC 228
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#define GCC_QUPV3_WRAP2_S4_CLK 229
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#define GCC_QUPV3_WRAP2_S4_CLK_SRC 230
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#define GCC_QUPV3_WRAP2_S4_DIV_CLK_SRC 231
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#define GCC_QUPV3_WRAP2_S5_CLK 232
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#define GCC_QUPV3_WRAP2_S5_CLK_SRC 233
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#define GCC_QUPV3_WRAP2_S6_CLK 234
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#define GCC_QUPV3_WRAP2_S6_CLK_SRC 235
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#define GCC_QUPV3_WRAP2_S7_CLK 236
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#define GCC_QUPV3_WRAP2_S7_CLK_SRC 237
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#define GCC_QUPV3_WRAP_0_M_AHB_CLK 238
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#define GCC_QUPV3_WRAP_0_S_AHB_CLK 239
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#define GCC_QUPV3_WRAP_1_M_AHB_CLK 240
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#define GCC_QUPV3_WRAP_1_S_AHB_CLK 241
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#define GCC_QUPV3_WRAP_2_M_AHB_CLK 242
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#define GCC_QUPV3_WRAP_2_S_AHB_CLK 243
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#define GCC_SDCC2_AHB_CLK 244
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#define GCC_SDCC2_APPS_CLK 245
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#define GCC_SDCC2_APPS_CLK_SRC 246
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#define GCC_SDCC4_AHB_CLK 247
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#define GCC_SDCC4_APPS_CLK 248
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#define GCC_SDCC4_APPS_CLK_SRC 249
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#define GCC_SYS_NOC_USB_AXI_CLK 250
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#define GCC_UFS_1_CARD_CLKREF_CLK 251
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#define GCC_UFS_CARD_AHB_CLK 252
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#define GCC_UFS_CARD_AXI_CLK 253
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#define GCC_UFS_CARD_AXI_CLK_SRC 254
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#define GCC_UFS_CARD_CLKREF_CLK 255
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#define GCC_UFS_CARD_ICE_CORE_CLK 256
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#define GCC_UFS_CARD_ICE_CORE_CLK_SRC 257
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#define GCC_UFS_CARD_PHY_AUX_CLK 258
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#define GCC_UFS_CARD_PHY_AUX_CLK_SRC 259
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#define GCC_UFS_CARD_RX_SYMBOL_0_CLK 260
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#define GCC_UFS_CARD_RX_SYMBOL_0_CLK_SRC 261
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#define GCC_UFS_CARD_RX_SYMBOL_1_CLK 262
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#define GCC_UFS_CARD_RX_SYMBOL_1_CLK_SRC 263
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#define GCC_UFS_CARD_TX_SYMBOL_0_CLK 264
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#define GCC_UFS_CARD_TX_SYMBOL_0_CLK_SRC 265
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#define GCC_UFS_CARD_UNIPRO_CORE_CLK 266
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#define GCC_UFS_CARD_UNIPRO_CORE_CLK_SRC 267
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#define GCC_UFS_PHY_AHB_CLK 268
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#define GCC_UFS_PHY_AXI_CLK 269
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#define GCC_UFS_PHY_AXI_CLK_SRC 270
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#define GCC_UFS_PHY_ICE_CORE_CLK 271
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#define GCC_UFS_PHY_ICE_CORE_CLK_SRC 272
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#define GCC_UFS_PHY_PHY_AUX_CLK 273
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#define GCC_UFS_PHY_PHY_AUX_CLK_SRC 274
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#define GCC_UFS_PHY_RX_SYMBOL_0_CLK 275
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#define GCC_UFS_PHY_RX_SYMBOL_0_CLK_SRC 276
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#define GCC_UFS_PHY_RX_SYMBOL_1_CLK 277
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#define GCC_UFS_PHY_RX_SYMBOL_1_CLK_SRC 278
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#define GCC_UFS_PHY_TX_SYMBOL_0_CLK 279
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#define GCC_UFS_PHY_TX_SYMBOL_0_CLK_SRC 280
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#define GCC_UFS_PHY_UNIPRO_CORE_CLK 281
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#define GCC_UFS_PHY_UNIPRO_CORE_CLK_SRC 282
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#define GCC_UFS_REF_CLKREF_CLK 283
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#define GCC_USB2_HS0_CLKREF_CLK 284
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#define GCC_USB2_HS1_CLKREF_CLK 285
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#define GCC_USB2_HS2_CLKREF_CLK 286
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#define GCC_USB2_HS3_CLKREF_CLK 287
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#define GCC_USB30_MP_MASTER_CLK 288
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#define GCC_USB30_MP_MASTER_CLK_SRC 289
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#define GCC_USB30_MP_MOCK_UTMI_CLK 290
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#define GCC_USB30_MP_MOCK_UTMI_CLK_SRC 291
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#define GCC_USB30_MP_MOCK_UTMI_POSTDIV_CLK_SRC 292
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#define GCC_USB30_MP_SLEEP_CLK 293
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#define GCC_USB30_PRIM_MASTER_CLK 294
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#define GCC_USB30_PRIM_MASTER_CLK_SRC 295
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#define GCC_USB30_PRIM_MOCK_UTMI_CLK 296
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#define GCC_USB30_PRIM_MOCK_UTMI_CLK_SRC 297
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#define GCC_USB30_PRIM_MOCK_UTMI_POSTDIV_CLK_SRC 298
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#define GCC_USB30_PRIM_SLEEP_CLK 299
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#define GCC_USB30_SEC_MASTER_CLK 300
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#define GCC_USB30_SEC_MASTER_CLK_SRC 301
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#define GCC_USB30_SEC_MOCK_UTMI_CLK 302
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#define GCC_USB30_SEC_MOCK_UTMI_CLK_SRC 303
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#define GCC_USB30_SEC_MOCK_UTMI_POSTDIV_CLK_SRC 304
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#define GCC_USB30_SEC_SLEEP_CLK 305
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#define GCC_USB34_PRIM_PHY_PIPE_CLK_SRC 306
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#define GCC_USB34_SEC_PHY_PIPE_CLK_SRC 307
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#define GCC_USB3_MP0_CLKREF_CLK 308
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#define GCC_USB3_MP1_CLKREF_CLK 309
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#define GCC_USB3_MP_PHY_AUX_CLK 310
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#define GCC_USB3_MP_PHY_AUX_CLK_SRC 311
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#define GCC_USB3_MP_PHY_COM_AUX_CLK 312
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#define GCC_USB3_MP_PHY_PIPE_0_CLK 313
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#define GCC_USB3_MP_PHY_PIPE_0_CLK_SRC 314
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#define GCC_USB3_MP_PHY_PIPE_1_CLK 315
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#define GCC_USB3_MP_PHY_PIPE_1_CLK_SRC 316
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#define GCC_USB3_PRIM_PHY_AUX_CLK 317
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#define GCC_USB3_PRIM_PHY_AUX_CLK_SRC 318
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#define GCC_USB3_PRIM_PHY_COM_AUX_CLK 319
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#define GCC_USB3_PRIM_PHY_PIPE_CLK 320
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#define GCC_USB3_PRIM_PHY_PIPE_CLK_SRC 321
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#define GCC_USB3_SEC_PHY_AUX_CLK 322
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#define GCC_USB3_SEC_PHY_AUX_CLK_SRC 323
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#define GCC_USB3_SEC_PHY_COM_AUX_CLK 324
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#define GCC_USB3_SEC_PHY_PIPE_CLK 325
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#define GCC_USB3_SEC_PHY_PIPE_CLK_SRC 326
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#define GCC_USB4_1_CFG_AHB_CLK 327
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#define GCC_USB4_1_DP_CLK 328
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#define GCC_USB4_1_MASTER_CLK 329
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#define GCC_USB4_1_MASTER_CLK_SRC 330
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#define GCC_USB4_1_PHY_DP_CLK_SRC 331
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#define GCC_USB4_1_PHY_P2RR2P_PIPE_CLK 332
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#define GCC_USB4_1_PHY_P2RR2P_PIPE_CLK_SRC 333
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#define GCC_USB4_1_PHY_PCIE_PIPE_CLK 334
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#define GCC_USB4_1_PHY_PCIE_PIPE_CLK_SRC 335
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#define GCC_USB4_1_PHY_PCIE_PIPE_MUX_CLK_SRC 336
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#define GCC_USB4_1_PHY_PCIE_PIPEGMUX_CLK_SRC 337
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#define GCC_USB4_1_PHY_RX0_CLK 338
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#define GCC_USB4_1_PHY_RX0_CLK_SRC 339
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#define GCC_USB4_1_PHY_RX1_CLK 340
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#define GCC_USB4_1_PHY_RX1_CLK_SRC 341
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#define GCC_USB4_1_PHY_SYS_CLK_SRC 342
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#define GCC_USB4_1_PHY_USB_PIPE_CLK 343
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#define GCC_USB4_1_SB_IF_CLK 344
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#define GCC_USB4_1_SB_IF_CLK_SRC 345
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#define GCC_USB4_1_SYS_CLK 346
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#define GCC_USB4_1_TMU_CLK 347
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#define GCC_USB4_1_TMU_CLK_SRC 348
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#define GCC_USB4_CFG_AHB_CLK 349
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#define GCC_USB4_CLKREF_CLK 350
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#define GCC_USB4_DP_CLK 351
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#define GCC_USB4_EUD_CLKREF_CLK 352
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#define GCC_USB4_MASTER_CLK 353
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#define GCC_USB4_MASTER_CLK_SRC 354
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#define GCC_USB4_PHY_DP_CLK_SRC 355
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#define GCC_USB4_PHY_P2RR2P_PIPE_CLK 356
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#define GCC_USB4_PHY_P2RR2P_PIPE_CLK_SRC 357
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#define GCC_USB4_PHY_PCIE_PIPE_CLK 358
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#define GCC_USB4_PHY_PCIE_PIPE_CLK_SRC 359
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#define GCC_USB4_PHY_PCIE_PIPE_MUX_CLK_SRC 360
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#define GCC_USB4_PHY_PCIE_PIPEGMUX_CLK_SRC 361
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#define GCC_USB4_PHY_RX0_CLK 362
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#define GCC_USB4_PHY_RX0_CLK_SRC 363
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#define GCC_USB4_PHY_RX1_CLK 364
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#define GCC_USB4_PHY_RX1_CLK_SRC 365
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#define GCC_USB4_PHY_SYS_CLK_SRC 366
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#define GCC_USB4_PHY_USB_PIPE_CLK 367
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#define GCC_USB4_SB_IF_CLK 368
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#define GCC_USB4_SB_IF_CLK_SRC 369
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#define GCC_USB4_SYS_CLK 370
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#define GCC_USB4_TMU_CLK 371
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#define GCC_USB4_TMU_CLK_SRC 372
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#define GCC_VIDEO_AHB_CLK 373
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#define GCC_VIDEO_AXI0_CLK 374
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#define GCC_VIDEO_AXI1_CLK 375
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#define GCC_VIDEO_CVP_THROTTLE_CLK 376
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#define GCC_VIDEO_VCODEC_THROTTLE_CLK 377
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#define GCC_VIDEO_XO_CLK 378
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#define GCC_AGGRE_UFS_CARD_AXI_HW_CTL_CLK 379
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#define GCC_AGGRE_UFS_PHY_AXI_HW_CTL_CLK 380
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#define GCC_UFS_CARD_AXI_HW_CTL_CLK 381
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#define GCC_UFS_CARD_ICE_CORE_HW_CTL_CLK 382
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#define GCC_UFS_CARD_PHY_AUX_HW_CTL_CLK 383
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#define GCC_UFS_CARD_UNIPRO_CORE_HW_CTL_CLK 384
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#define GCC_UFS_PHY_AXI_HW_CTL_CLK 385
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#define GCC_UFS_PHY_ICE_CORE_HW_CTL_CLK 386
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#define GCC_UFS_PHY_PHY_AUX_HW_CTL_CLK 387
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#define GCC_UFS_PHY_UNIPRO_CORE_HW_CTL_CLK 388
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/* GCC resets */
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#define GCC_EMAC0_BCR 0
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#define GCC_EMAC1_BCR 1
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#define GCC_PCIE_0_LINK_DOWN_BCR 2
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#define GCC_PCIE_0_NOCSR_COM_PHY_BCR 3
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#define GCC_PCIE_0_PHY_BCR 4
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#define GCC_PCIE_0_PHY_NOCSR_COM_PHY_BCR 5
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#define GCC_PCIE_0_TUNNEL_BCR 6
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#define GCC_PCIE_1_LINK_DOWN_BCR 7
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#define GCC_PCIE_1_NOCSR_COM_PHY_BCR 8
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#define GCC_PCIE_1_PHY_BCR 9
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#define GCC_PCIE_1_PHY_NOCSR_COM_PHY_BCR 10
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#define GCC_PCIE_1_TUNNEL_BCR 11
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#define GCC_PCIE_2A_BCR 12
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#define GCC_PCIE_2A_LINK_DOWN_BCR 13
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#define GCC_PCIE_2A_NOCSR_COM_PHY_BCR 14
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#define GCC_PCIE_2A_PHY_BCR 15
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#define GCC_PCIE_2A_PHY_NOCSR_COM_PHY_BCR 16
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#define GCC_PCIE_2B_BCR 17
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#define GCC_PCIE_2B_LINK_DOWN_BCR 18
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#define GCC_PCIE_2B_NOCSR_COM_PHY_BCR 19
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#define GCC_PCIE_2B_PHY_BCR 20
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#define GCC_PCIE_2B_PHY_NOCSR_COM_PHY_BCR 21
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#define GCC_PCIE_3A_BCR 22
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#define GCC_PCIE_3A_LINK_DOWN_BCR 23
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#define GCC_PCIE_3A_NOCSR_COM_PHY_BCR 24
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#define GCC_PCIE_3A_PHY_BCR 25
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#define GCC_PCIE_3A_PHY_NOCSR_COM_PHY_BCR 26
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#define GCC_PCIE_3B_BCR 27
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#define GCC_PCIE_3B_LINK_DOWN_BCR 28
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|
#define GCC_PCIE_3B_NOCSR_COM_PHY_BCR 29
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|
#define GCC_PCIE_3B_PHY_BCR 30
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|
#define GCC_PCIE_3B_PHY_NOCSR_COM_PHY_BCR 31
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|
#define GCC_PCIE_4_BCR 32
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|
#define GCC_PCIE_4_LINK_DOWN_BCR 33
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|
#define GCC_PCIE_4_NOCSR_COM_PHY_BCR 34
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|
#define GCC_PCIE_4_PHY_BCR 35
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|
#define GCC_PCIE_4_PHY_NOCSR_COM_PHY_BCR 36
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|
#define GCC_PCIE_PHY_CFG_AHB_BCR 37
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#define GCC_PCIE_PHY_COM_BCR 38
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|
#define GCC_PCIE_RSCC_BCR 39
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|
#define GCC_QUSB2PHY_HS0_MP_BCR 40
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|
#define GCC_QUSB2PHY_HS1_MP_BCR 41
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|
#define GCC_QUSB2PHY_HS2_MP_BCR 42
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|
#define GCC_QUSB2PHY_HS3_MP_BCR 43
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|
#define GCC_QUSB2PHY_PRIM_BCR 44
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|
#define GCC_QUSB2PHY_SEC_BCR 45
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|
#define GCC_SDCC2_BCR 46
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|
#define GCC_SDCC4_BCR 47
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|
#define GCC_UFS_CARD_BCR 48
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|
#define GCC_UFS_PHY_BCR 49
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|
#define GCC_USB2_PHY_PRIM_BCR 50
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|
#define GCC_USB2_PHY_SEC_BCR 51
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|
#define GCC_USB30_MP_BCR 52
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|
#define GCC_USB30_PRIM_BCR 53
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|
#define GCC_USB30_SEC_BCR 54
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|
#define GCC_USB3_DP_PHY_PRIM_BCR 55
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|
#define GCC_USB3_DP_PHY_SEC_BCR 56
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|
#define GCC_USB3_PHY_PRIM_BCR 57
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|
#define GCC_USB3_PHY_SEC_BCR 58
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|
#define GCC_USB3_UNIPHY_MP0_BCR 59
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|
#define GCC_USB3_UNIPHY_MP1_BCR 60
|
|
#define GCC_USB3PHY_PHY_PRIM_BCR 61
|
|
#define GCC_USB3PHY_PHY_SEC_BCR 62
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|
#define GCC_USB3UNIPHY_PHY_MP0_BCR 63
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|
#define GCC_USB3UNIPHY_PHY_MP1_BCR 64
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|
#define GCC_USB4_1_BCR 65
|
|
#define GCC_USB4_1_DP_PHY_PRIM_BCR 66
|
|
#define GCC_USB4_1_DPPHY_AUX_BCR 67
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|
#define GCC_USB4_1_PHY_PRIM_BCR 68
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|
#define GCC_USB4_BCR 69
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|
#define GCC_USB4_DP_PHY_PRIM_BCR 70
|
|
#define GCC_USB4_DPPHY_AUX_BCR 71
|
|
#define GCC_USB4_PHY_PRIM_BCR 72
|
|
#define GCC_USB4PHY_1_PHY_PRIM_BCR 73
|
|
#define GCC_USB4PHY_PHY_PRIM_BCR 74
|
|
#define GCC_USB_PHY_CFG_AHB2PHY_BCR 75
|
|
#define GCC_VIDEO_BCR 76
|
|
#define GCC_VIDEO_AXI0_CLK_ARES 77
|
|
#define GCC_VIDEO_AXI1_CLK_ARES 78
|
|
|
|
/* GCC GDSCs */
|
|
#define PCIE_0_TUNNEL_GDSC 0
|
|
#define PCIE_1_TUNNEL_GDSC 1
|
|
#define PCIE_2A_GDSC 2
|
|
#define PCIE_2B_GDSC 3
|
|
#define PCIE_3A_GDSC 4
|
|
#define PCIE_3B_GDSC 5
|
|
#define PCIE_4_GDSC 6
|
|
#define UFS_CARD_GDSC 7
|
|
#define UFS_PHY_GDSC 8
|
|
#define USB30_MP_GDSC 9
|
|
#define USB30_PRIM_GDSC 10
|
|
#define USB30_SEC_GDSC 11
|
|
#define EMAC_0_GDSC 12
|
|
#define EMAC_1_GDSC 13
|
|
#define USB4_1_GDSC 14
|
|
#define USB4_GDSC 15
|
|
#define HLOS1_VOTE_MMNOC_MMU_TBU_HF0_GDSC 16
|
|
#define HLOS1_VOTE_MMNOC_MMU_TBU_HF1_GDSC 17
|
|
#define HLOS1_VOTE_MMNOC_MMU_TBU_SF0_GDSC 18
|
|
#define HLOS1_VOTE_MMNOC_MMU_TBU_SF1_GDSC 19
|
|
#define HLOS1_VOTE_TURING_MMU_TBU0_GDSC 20
|
|
#define HLOS1_VOTE_TURING_MMU_TBU1_GDSC 21
|
|
#define HLOS1_VOTE_TURING_MMU_TBU2_GDSC 22
|
|
#define HLOS1_VOTE_TURING_MMU_TBU3_GDSC 23
|
|
|
|
#endif
|